公开(公告)号：US11171086B2

公开(公告)日：2021-11-09

申请号：US16700485

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji Kubo ,  Koichi Ando ,  Eiji Io ,  Hideyuki Tajima ,  Tetsuya Iida

IPC: H01L23/522 ,  H01L23/373 ,  H01L21/768 ,  H01L27/06

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

公开(公告)号：US09608108B2

公开(公告)日：2017-03-28

申请号：US14835373

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Mikio Tsujiuchi ,  Kouji Tanaka ,  Yasuki Yoshihisa ,  Shunji Kubo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7835 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816

Abstract: A semiconductor substrate has a main surface with an n type offset region having a trench portion formed of a plurality of trenches extending in a direction from an n+ drain region toward an n+ source region. The plurality of trenches each have a conducting layer therein extending in the main surface in the direction from the n+ drain region toward the n+ source region.

公开(公告)号：US09257551B2

公开(公告)日：2016-02-09

申请号：US14594034

申请日：2015-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji Kubo

IPC: H01L29/66 ,  H01L29/76 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0847 ,  H01L29/0615 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).