公开(公告)号：US07406579B2

公开(公告)日：2008-07-29

申请号：US11160184

申请日：2005-08-19

申请人： Rafael Blanco ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Rafael Blanco ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F12/0886 ,  G06F12/0864

摘要： The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficiency for communicating with the memory. In particular, a register can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache, multiple ways of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task, a processor, and/or a performance evaluation.

摘要翻译： 本发明提供了选择性地改变存储器的线宽，即选择存储器的多条线宽之一。 选择的线宽用于与一个或多个处理器进行通信。 这提高了与内存通信的灵活性和效率。 特别地，可以基于期望的线宽来设置寄存器，并且随后在将数据定位在存储器中时使用。 所选线宽可以与存储器中的每个数据块相关联，以允许同时使用多个线宽。 当在缓存中实现时，高速缓存的多种方式可以被处理为一组以在单个存储器操作期间提供数据。 线宽可以根据任务，处理器和/或性能评估而变化。

公开(公告)号：US08612815B2

公开(公告)日：2013-12-17

申请号：US13327847

申请日：2011-12-16

申请人： Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G01R31/28

CPC分类号： G01R31/31813 ,  G01R31/3187

摘要： Disclosed are integrated circuits that incorporate an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. Specifically, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal.

摘要翻译： 公开了集成电路，其包括具有内置自检（BIST）架构的异步电路，其使用用于高速测试的握手协议来检测卡住的故障。 具体来说，测试模式发生器将测试模式应用于异步电路，分析仪分析输出测试数据。 握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换 的测试模式确认信号。 可以通过切换测试模式确认信号来强制产生该单个脉冲。

公开(公告)号：US07489163B2

公开(公告)日：2009-02-10

申请号：US11869921

申请日：2007-10-10

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

公开(公告)号：US07065733B2

公开(公告)日：2006-06-20

申请号：US10725712

申请日：2003-12-02

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvié ,  Christ pher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvié ,  Christ pher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  H03K17/693

CPC分类号： G06F17/5054

摘要： A method and system for modifying the function of a state machine having a programmable logic device. The method includes the steps of modifying a high-level design of the state machine to obtain a modified high-level design of the state machine with a modified function; generating a programmable logic device netlist from differences in the high-level design and the high-level modified design; and installing the modified function into the state machine by programming the programmable logic device based on the programmable logic device netlist.

摘要翻译： 一种用于修改具有可编程逻辑器件的状态机的功能的方法和系统。 该方法包括以下步骤：修改状态机的高级设计，以获得具有修改功能的状态机的修改的高级设计; 从高级设计和高级修改设计的差异中产生可编程逻辑器件网表; 并通过基于可编程逻辑器件网表对可编程逻辑器件进行编程，将修改后的功能安装到状态机中。

公开(公告)号：US20120168416A1

公开(公告)日：2012-07-05

申请号：US12984638

申请日：2011-01-05

申请人： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H05B3/00 ,  G06F17/50

CPC分类号： H05B1/0227 ,  G05D23/1934

摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。

公开(公告)号：US20080290896A1

公开(公告)日：2008-11-27

申请号：US12185467

申请日：2008-08-04

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) system that includes an RLA and a programmer for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks. The programmer contains software that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

摘要翻译： 可重构逻辑阵列（RLA）系统，其包括RLA和用于在循环基础上重新编程RLA的编程器。 需要比RLA中包含的逻辑量​​大的函数（F）被划分为多个功能块。 程序员包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

公开(公告)号：US06954085B2

公开(公告)日：2005-10-11

申请号：US10605603

申请日：2003-10-13

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G06F15/78 ,  H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is re-configuring function region with the next functional block and re-configuring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

摘要翻译： 一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。 需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。 程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。 然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。 当程序员使用下一个功能块重新配置功能区域并且重新配置用于接收下一个功能块的输出的一个存储区域时，从当前功能块传递到下一个功能块的数据被保存在 其他存储区域。

公开(公告)号：US06253299B1

公开(公告)日：2001-06-26

申请号：US09224793

申请日：1999-01-04

申请人： Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F1200

CPC分类号： G06F9/30112 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/30138 ,  G06F12/0875

摘要： A structure and method for processing data comprises a processing unit having a base cache, base registers having a base width and being operatively connected to the processing unit, and virtual cache registers having a virtual width and being located in the base cache and operatively connected to the processing unit, wherein a base processing precision of the processing system is determined by the base width of the base registers and a selectable enhanced processing precision is determined by the virtual width of the virtual cache registers, wherein the base registers store base instructions and data and the virtual cache registers store enhanced data, the virtual width being greater than the base width, and wherein the base cache includes tags identifying a portion of the base cache as the virtual registers, the virtual cache registers being accessible by the processing unit only for execution of enhanced instructions for providing the enhanced processing precision.

摘要翻译： 用于处理数据的结构和方法包括具有基本高速缓存，具有基本宽度并且可操作地连接到处理单元的基本寄存器的处理单元和具有虚拟宽度并位于基本高速缓存中并可操作地连接到 所述处理单元，其中所述处理系统的基本处理精度由所述基本寄存器的基本宽度确定，并且可选择的增强处理精度由所述虚拟高速缓存寄存器的虚拟宽度确定，其中所述基本寄存器存储基本指令和数据 并且所述虚拟高速缓存寄存器存储增强数据，所述虚拟宽度大于所述基本宽度，并且其中所述基本高速缓存包括标识所述基本高速缓存的一部分作为所述虚拟寄存器的标签，所述虚拟高速缓存寄存器仅由所述处理单元访问 执行增强的指令以提供增强的处理精度。

公开(公告)号：US20130159803A1

公开(公告)日：2013-06-20

申请号：US13327847

申请日：2011-12-16

申请人： Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： G01R31/28

CPC分类号： G01R31/31813 ,  G01R31/3187

摘要： Disclosed are embodiments of an integrated circuit that incorporates an asynchronous circuit with a built-in self-test (BIST) architecture using a handshaking protocol for at-speed testing to detect stuck-at faults. In the embodiments, a test pattern generator applies test patterns to an asynchronous circuit and an analyzer analyzes the output test data. The handshaking protocol is achieved through the use of a single pulse generator, which applies a single pulse to the test pattern generator to force switching of the test pattern request signal and, thereby to control application of the test patterns to the asynchronous circuit and subsequent switching of the test pattern acknowledge signal. Generation of this single pulse can in turn be forced by the switching of the test pattern acknowledge signal. Optionally, a time constraint can be added to the capture of the output test data to allow for detection of delay faults.

摘要翻译： 公开了集成电路的实施例，该集成电路结合具有内置自检（BIST）架构的异步电路，使用用于高速测试的握手协议来检测卡住故障。 在实施例中，测试模式发生器将测试模式应用于异步电路，分析器分析输出测试数据。 握手协议通过使用单个脉冲发生器来实现，该单个脉冲发生器向测试模式发生器施加单个脉冲以强制测试模式请求信号的切换，从而控制测试模式对异步电路的应用和随后的切换 的测试模式确认信号。 可以通过切换测试模式确认信号来强制产生该单个脉冲。 可选地，可以将时间约束添加到捕获输出测试数据以允许检测延迟故障。

公开(公告)号：US07750670B2

公开(公告)日：2010-07-06

申请号：US12185467

申请日：2008-08-04

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC分类号： H03K19/173

CPC分类号： H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

摘要： A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.

摘要翻译： 具有逻辑容量并被配置为处理具有超过RLA的逻辑容量的总逻辑要求的功能的可重构逻辑阵列（RLA）。 RLA包括第一和第二存储区域以及位于第一和第二存储区域之间的多个可编程逻辑元件。 当功能被解析成多个功能块时，该配置允许RLA通过在RLA内沿交替方向依次处理功能块来处理功能，使用多个可编程逻辑元件来顺序地处理每个功能块和 使用第一和第二存储区域临时保持该功能块的输入和输出。