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公开(公告)号：US07582956B2
公开(公告)日：2009-09-01
申请号：US11693141
申请日：2007-03-29
IPC分类号： H01L23/495
CPC分类号： H01L23/49562 , H01L23/3121 , H01L23/3185 , H01L23/49531 , H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。
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公开(公告)号：US07154168B2
公开(公告)日：2006-12-26
申请号：US10702792
申请日：2003-11-05
IPC分类号： H01L23/495 , H01L23/498
CPC分类号： H01L23/49562 , H01L23/3121 , H01L23/3185 , H01L23/49531 , H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
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公开(公告)号：US07215011B2
公开(公告)日：2007-05-08
申请号：US11213182
申请日：2005-08-25
IPC分类号： H01L23/495
CPC分类号： H01L23/49562 , H01L23/3121 , H01L23/3185 , H01L23/49531 , H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。
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公开(公告)号：US06949410B2
公开(公告)日：2005-09-27
申请号：US10607633
申请日：2003-06-27
IPC分类号： H01L23/48 , H01L21/76 , H01L23/31 , H01L23/495 , H01L23/52 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/49562 , H01L23/3121 , H01L23/3185 , H01L23/49531 , H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。
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公开(公告)号：US06720642B1
公开(公告)日：2004-04-13
申请号：US09464885
申请日：1999-12-16
IPC分类号： H01L23495
CPC分类号： H01L23/49562 , H01L23/3121 , H01L23/3185 , H01L23/49531 , H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54486 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
摘要翻译： 一种芯片器件，包括引线框架，模具和模具化合物。 模具的背面被金属化并且通过在模具化合物中限定的窗口暴露，当模具化合物耦合到引线框架时封装模具。 引线框架上的引线耦合到管芯上的源极和栅极端子，而管芯的金属化背面用作漏极端子。
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6.发明授权Method for maintaining solder thickness in flipchip attach packaging processes 有权用于在倒装芯片附接包装工艺中保持焊料厚度的方法公开(公告)号：US06943434B2
公开(公告)日：2005-09-13
申请号：US10678010
申请日：2003-10-02
IPC分类号： H01L21/60 , H01L23/31 , H01L23/485 , H01L23/495 , H01L23/544
CPC分类号： H01L23/49582 , H01L23/3107 , H01L23/49562 , H01L23/49586 , H01L23/544 , H01L24/10 , H01L24/13 , H01L24/81 , H01L2223/54473 , H01L2223/54486 , H01L2224/05568 , H01L2224/05573 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15747 , H01L2924/181 , H01L2924/18161 , H01L2924/18301 , H01L2924/30107 , H01L2924/351 , H01L2224/45099 , H01L2924/00 , H01L2224/81205 , H01L2224/05599
摘要： A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.
摘要翻译： 描述了一种用于半导体器件的封装组件及其制造方法。 本发明在新的倒装芯片封装方法中提供了非Pb凸点设计。 该设计采用螺柱形式的特殊导电材料，而不是含Pb的焊球。 该配置在管芯和引线框架之间保持期望的焊料厚度，并通过限制引线框架侧上的焊料润湿性而形成高的间隙。 这种结构也吸收任何应力并保护模具免受开裂。 本发明还提供了制造这种半导体封装的方法。
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公开(公告)号：US07439613B2
公开(公告)日：2008-10-21
申请号：US10841656
申请日：2004-05-06
IPC分类号： H01L21/44
CPC分类号： H01L23/49861 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45147
摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.
摘要翻译： 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。 管芯附着表面和引线表面可以在不同的平面上。
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公开(公告)号：US20080213946A1
公开(公告)日：2008-09-04
申请号：US12118222
申请日：2008-05-09
IPC分类号： H01L21/60
CPC分类号： H01L23/49861 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45147
摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.
摘要翻译： 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯位于管芯附着区域上，半导体管芯与引线电耦合。 管芯附着表面和引线表面可以在不同的平面上。
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公开(公告)号：US07682877B2
公开(公告)日：2010-03-23
申请号：US12118222
申请日：2008-05-09
IPC分类号： H01L21/00
CPC分类号： H01L23/49861 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/48091 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45147
摘要： A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.
摘要翻译： 公开了一种半导体管芯封装。 在一个实施例中，半导体管芯封装具有衬底。 它包括（i）引线框架结构，其包括具有管芯附接表面的管芯附着区域和具有引线表面的引线，以及（ii）模制材料。 裸片附着表面和引线表面通过模制材料暴露。 半导体管芯在管芯附着区域上，并且半导体管芯电耦合到引线。 管芯附着表面和引线表面可以在不同的平面上。
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公开(公告)号：US07842555B2
公开(公告)日：2010-11-30
申请号：US12349140
申请日：2009-01-06
CPC分类号： H01L23/562 , H01L23/49562 , H01L23/49575 , H01L24/97 , H01L25/072 , H01L2224/16245 , H01L2224/32245 , H01L2224/73253 , H01L2224/94 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H02M3/00 , H01L2224/83 , H01L2224/81 , H01L2924/00
摘要： An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.
摘要翻译： 集成晶体管模块包括限定至少一个低侧焊盘和至少一个高侧焊盘的引线框架。 引线框架的台阶部分将低边和高边平台机械地和电气地互连。 低侧晶体管安装在低侧焊盘上，其漏极电连接到低侧焊盘。 高侧晶体管安装在高侧焊盘上，其源极与高侧焊盘电连接。
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