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公开(公告)号：US20060120176A1
公开(公告)日：2006-06-08
申请号：US11235540
申请日：2005-09-27
IPC分类号： G11C7/06
CPC分类号： G11C29/025 , G11C8/08 , G11C11/401 , G11C29/02 , G11C2029/1202
摘要： An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.
摘要翻译： 集成半导体存储器包括通过相应的第一可控开关和相应的第三可控开关连接到第一电压电位的字线，以及经由相应的第二可控开关连接到第二电压电位的字线。 为了测试字线之一是否经由其相应的第一和第三可控开关连接到第一电压电位，所述字线之一经由相应的第二可控开关和驱动器线连接到比较器电路。 在相应的第一和第三可控开关已经被控制为导通状态之后，在集成半导体存储器的测试操作状态下，将相应的第二可控开关控制在导通状态，并且字线上的电位状态由 比较器电路。 评估结果通过评估信号馈送到外部数据终端。
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2.发明申请Integrated semiconductor memory and method for operating a semiconductor memory 失效用于操作半导体存储器的集成半导体存储器和方法公开(公告)号：US20060193168A1
公开(公告)日：2006-08-31
申请号：US11331365
申请日：2006-01-13
CPC分类号： G11C11/404 , H01L27/10885
摘要： An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor. The resultant increase in the signal strength makes the semiconductor memory insensitive toward signal corruptions which arise for example in the case of operating voltages at different levels for selection transistors and for transistors in the signal amplifier.
摘要翻译： 集成半导体存储器件包括各自具有选择晶体管和存储电容器的存储单元。 这种类型的存储单元通常通过读出放大器中与存储器单元连接的位线的电位进行读取，其中互补的第二位线的电位和识别的电压差被放大。 根据本发明的半导体存储器提供了未连接到选择晶体管以连接到互补的第二位线的电容器电极。 结果，对于具有相同幅度的工作电压，由于现在由读出放大器输出的两个相互扩展的电位用于偏置存储电容器，所以可以将大量的电荷存储在存储电容器中。 信号强度的增加使得半导体存储器对信号损坏不敏感，例如在用于选择晶体管的不同电平的操作电压和信号放大器中的晶体管的情况下。
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3.发明申请Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory 失效集成半导体存储器和用于电应力集成半导体存储器的方法公开(公告)号：US20050194614A1
公开(公告)日：2005-09-08
申请号：US11061087
申请日：2005-02-18
IPC分类号： G11C11/407 , G11C29/00 , G11C29/02 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L29/73 , H01L29/739 , H01L29/74
CPC分类号： G11C29/025 , G11C29/02 , H01L27/105 , H01L27/10891
摘要： Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.
摘要翻译： 半导体存储器（1）具有分段字线（5a，5b），其在每种情况下具有由导电金属制成的主字线（10a，10b）和多个互连片段（15a，15b） ），其耦合到主字线（10a，10b），其通过至少一个接触孔填充物（11）在每种情况下耦合到相应的主字线（10a，10b）。 如果接触孔填充物（11）中的一个有缺陷或高电阻，则会发生半导体存储器的功能错误。 两个相应字线（5a，5b）的互连段（15a，5b）可以借助于开关单元（20）成对地短路，由此通过 接触孔填充物（11）可以用于电接触接触孔填充物（11）。 因此，分段字线的接触孔填充的电应力成为可能。
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4.发明申请Integrated semiconductor memory device and method for operating an integrated semiconductor memory device 有权用于操作集成半导体存储器件的集成半导体存储器件和方法公开(公告)号：US20050195638A1
公开(公告)日：2005-09-08
申请号：US11071590
申请日：2005-03-04
IPC分类号： G11C7/12 , G11C11/00 , G11C11/4094
CPC分类号： G11C11/4094 , G11C7/02 , G11C7/12
摘要： An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.
摘要翻译： 集成半导体存储器件包括具有第一位线和第二位线（BL，/ BL）的存储单元阵列（B 1），可控电阻器（SW）和控制单元（100），其被配置为控制可控电阻器 。 在集成半导体存储器件的第一操作状态下，第一和第二位线经由第一可控开关（ET 1）彼此连接，并且还经由设置为低电阻的可控电阻（SW）连接， 涉及施加中间电压（V BAT）的连接（A 10），其中中压的电压电平为第一和第二电压电位之间的算术平均值 VBLH，VBLL）。 由于控制单元在集成半导体存储器件的第一操作状态下将可控电阻短暂地设置为非常低的电阻，所以第一和第二位线所需的时间段需要采用中间电压（V < SUB> BLEQ ）被缩短。 因此，将第一和第二位线的充电速度降低到中间电压的电容耦合影响的影响显着减小。
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公开(公告)号：US20050248996A1
公开(公告)日：2005-11-10
申请号：US11123226
申请日：2005-05-06
申请人： Ralf Schneider , Stephan Schroder , Manfred Proll , Jorg Kliewer
发明人： Ralf Schneider , Stephan Schroder , Manfred Proll , Jorg Kliewer
IPC分类号： G05F1/595 , G11C5/14 , G11C7/00 , G11C11/4074
CPC分类号： G11C11/4074 , G11C5/145
摘要： An integrated circuit includes an input terminal (IN) for application of a supply voltage (Vext) and an output terminal (A) for generation of an output voltage (Vout). A first branch including a first controllable resistance (T1) and a second branch including a charge pump (10) and a second controllable resistance (T2) are connected between the input terminal (IN) and the output terminal (A). A control circuit (20) alters the resistance values of the first and second controllable resistances (T1, T2) in a manner dependent on a ratio of an actual value (Vout) of the output voltage to a desired value (VSout) of the output voltage and a ratio of an actual value (Vext) of the supply voltage to a desired value (VSext) of the supply voltage. As a result, the output voltage (Vout) can be stabilized to the desired value (VSout) virtually independently of fluctuations of the supply voltage.
摘要翻译： 集成电路包括用于施加电源电压（Vext）的输入端（IN）和用于产生输出电压（Vout）的输出端子（A）。 包括第一可控电阻（T 1）和包括电荷泵（10）和第二可控电阻（T 2）的第二分支的第一分支连接在输入端（IN）和输出端（A）之间。 控制电路（20）以取决于输出电压的实际值（Vout）与期望值（VSout）的比值的方式改变第一和第二可控电阻（T 1，T 2）的电阻值 输出电压和电源电压的实际值（Vext）与电源电压的期望值（VSext）的比率。 结果，输出电压（Vout）可以实际上独立于电源电压的波动而稳定到期望值（VSout）。
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公开(公告)号：US20050135163A1
公开(公告)日：2005-06-23
申请号：US11008159
申请日：2004-12-10
申请人： Ralf Schneider , Jurgen Auge , Stephan Schroder , Manfred Proll
发明人： Ralf Schneider , Jurgen Auge , Stephan Schroder , Manfred Proll
IPC分类号： G11C7/00 , G11C11/407 , G11C16/04 , G11C29/44
CPC分类号： G11C29/44 , G11C11/401 , G11C2029/1208 , G11C2029/4402
摘要： An integrated circuit includes a programming circuit (10) for generating programming signals (PS1, . . . , PS4) with a first input terminal (E1) for applying a control voltage (ES), a second input terminal (E2) for applying a reference voltage (Vref), a storage circuit (30) with programmable switches (35, . . . , 38) and output terminals (A1, . . . , A4). The programming circuit in each case generates a programming signal (PS1, . . . , PS4) when the control voltage (ES) exceeds a predefined threshold voltage formed from the reference voltage. The number of programming signals (PS1, . . . , PS4) is dependent on the magnitude of the threshold voltage exceeded by the control voltage (ES). The programming signals are used for programming the programmable switches (35, . . . , 38). The programming state of the programmable switches can be read out via the output terminals (A1, . . . , A4) of the integrated circuit. The integrated circuit enables the storage of external operating parameters of the integrated circuit.
摘要翻译： 一种集成电路包括用于产生编程信号（PS 1，...，PS 4）的编程电路（10），其具有用于施加控制电压（ES）的第一输入端（E 1），第二输入端 ），用于施加参考电压（Vref），具有可编程开关（35 ...，38）和输出端子（A 1，...，A 4）的存储电路（30）。 当控制电压（ES）超过由参考电压形成的预定阈值电压时，编程电路在每种情况下产生编程信号（PS 1，...，PS 4）。 编程信号（PS 1，...，PS 4）的数量取决于超过控制电压（ES）的阈值电压的大小。 编程信号用于对可编程开关（35，...，38）进行编程。 可编程开关的编程状态可以通过集成电路的输出端子（A 1，...，A 4）读出。 集成电路可以存储集成电路的外部工作参数。
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公开(公告)号：US20070247944A1
公开(公告)日：2007-10-25
申请号：US11739444
申请日：2007-04-24
CPC分类号： G11C7/04 , G11C11/406 , G11C11/40626 , G11C29/028 , G11C2029/5002 , G11C2211/4061
摘要： An integrated semiconductor memory with refreshing of memory cells includes a temperature sensor to detect a chip temperature of the integrated semiconductor memory, a connection to apply a command signal, a frequency generation unit to generate a frequency signal, and a memory cell to store a data item, the stored data item being refreshed at the frequency of the frequency signal. The frequency generation unit generates the frequency signal at a first frequency on the basis of a chip temperature detected by the temperature sensor when a first state of the command signal is applied and the frequency generation unit generates the frequency signal at a second frequency, which is changed in comparison with the first frequency, at the same chip temperature when a second state of the command signal is applied.
摘要翻译： 具有刷新存储单元的集成半导体存储器包括用于检测集成半导体存储器的芯片温度的温度传感器，应用命令信号的连接，产生频率信号的频率产生单元和用于存储数据的存储单元 项目，以频率信号的频率刷新存储的数据项。 当施加指令信号的第一状态时，频率产生单元基于由温度传感器检测到的芯片温度，以第一频率产生频率信号，并且频率产生单元以第二频率产生频率信号 在施加命令信号的第二状态时，以相同的芯片温度与第一频率相比变化。
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公开(公告)号：US20050018507A1
公开(公告)日：2005-01-27
申请号：US10892251
申请日：2004-07-16
IPC分类号： G11C7/10 , G11C7/12 , G11C11/4094 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/109 , G11C7/04 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C11/4096
摘要： A circuit for controlling an access to an integrated memory includes a command decoder for receiving at least one external command for an access to the memory. An access controller is connected to the command decoder for receiving internal command signals, which are output by the command decoder. In the course of a memory access, the command decoder outputs a precharge command signal for precharging a row of the memory cell array of the integrated memory. A control circuit, which can determine a temperature of the memory, is designed to temporally variably influence the transmission of the precharge command signal of the command decoder to the access controller in a manner dependent on the temperature of the memory. The write recovery time tWR can be retained even for higher operating frequencies of the memory.
摘要翻译： 用于控制对集成存储器的访问的电路包括命令解码器，用于接收至少一个外部命令以访问存储器。 访问控制器连接到命令解码器，用于接收由命令解码器输出的内部命令信号。 在存储器访问的过程中，命令解码器输出用于对集成存储器的存储单元阵列的行进行预充电的预充电命令信号。 可以确定存储器的温度的控制电路被设计为以取决于存储器的温度的方式在时间上可变地影响命令解码器的预充电命令信号到访问控制器的传输。 即使对于存储器的较高工作频率，也可以保留写恢复时间tWR。
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9.发明申请Arrangement for determining a temperature loading of an integrated circuit and method 有权用于确定集成电路的温度负载的方案和方法公开(公告)号：US20050226309A1
公开(公告)日：2005-10-13
申请号：US11009969
申请日：2004-12-10
申请人： Manfred Proll , Jurgen Auge , Stephan Schroder , Thomas Huber
发明人： Manfred Proll , Jurgen Auge , Stephan Schroder , Thomas Huber
IPC分类号： G01K1/02 , G01K7/01 , H01L23/544 , G01K7/00
CPC分类号： H01L22/34 , G01K1/024 , G01K7/01 , H01L2924/0002 , H01L2924/00
摘要： In an arrangement for determining a temperature loading during a soldering process, a semiconductor chip (1) comprises at least one contact (2) to be soldered or is electrically conductively connected to at least one contact (14d) to be soldered that is situated outside the semiconductor chip. The semiconductor chip (1) furthermore comprises a temperature sensor device (3), which determines a measurement quantity corresponding to the temperature. A processing device (4, 5) has an analog-to-digital converter (5), which is electrically conductively connected to the temperature sensor device (3) and converts the measurement quantity into at least one storable signal that represents the temperature loading. A voltage supply device (10), which is electrically conductively connected to the temperature sensor device (3) and the processing device (4, 5), supplies these components with an operating voltage. A data memory (6) serves for storing the at least one storable signal. An electrical line (7, 11) connected to the data memory (6) serves for outputting the stored signal. As a result, it is possible to monitor temperature loadings of the semiconductor chip also outside the sphere of influence of the semiconductor manufacturer.
摘要翻译： 在用于确定在焊接过程期间的温度负载的布置中，半导体芯片（1）包括至少一个要被焊接的触点（2）或者导电地连接到至少一个待焊接的触点（14d） 在半导体芯片之外。 半导体芯片（1）还包括温度传感器装置（3），其确定与温度相对应的测量量。 处理装置（4,5）具有电导体连接到温度传感器装置（3）的模拟数字转换器（5），并将测量量转换成表示温度负载的至少一个可存储信号。 与温度传感器装置（3）和处理装置（4,5）导电连接的电压供给装置（10）向这些部件提供工作电压。 数据存储器（6）用于存储至少一个可存储信号。 连接到数据存储器（6）的电线（7,11）用于输出所存储的信号。 因此，可以在半导体制造商的影响范围之外监视半导体芯片的温度负载。
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公开(公告)号：US20050174863A1
公开(公告)日：2005-08-11
申请号：US11053659
申请日：2005-02-09
申请人： Manfred Proll , Johann Pfeiffer , Stephan Schroder , Arndt Gruber , Georg Eggers
发明人： Manfred Proll , Johann Pfeiffer , Stephan Schroder , Arndt Gruber , Georg Eggers
CPC分类号： G11C29/50 , G11C7/1006 , G11C11/401 , G11C29/36 , G11C29/50016 , G11C29/80
摘要： An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.
摘要翻译： 一种集成半导体存储器，包括可以经由第一和第二字线驱动并可由冗余存储器单元代替的存储单元。 在第一存储单元类型中，可以对应于存在于数据输入端的数据存储数据。 在第二存储单元类型的存储单元中，数据可以相对于存在于数据输入端的数据反转存储。 集成半导体存储器包括用于数据反转的电路，其中数据被写入冗余存储单元，相对于存在于数据输入端的数据而被反转，如果有缺陷的存储单元和替换它的冗余存储单元位于不同的 位线的字线条扭曲，并且如果不良存储器单元和替换它的冗余存储器单元与不同的存储器单元类型相关联。
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