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    Folded memory modules
    2.
    发明授权
    Folded memory modules 有权

    公开(公告)号：US12147367B2

    公开(公告)日：2024-11-19

    申请号：US18355660

    申请日：2023-07-20

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/40 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    High Performance, High Capacity Memory Modules and Systems
    4.
    发明申请
    High Performance, High Capacity Memory Modules and Systems 有权

    公开(公告)号：US20230138512A1

    公开(公告)日：2023-05-04

    申请号：US17989838

    申请日：2022-11-18

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

    FOLDED MEMORY MODULES
    6.
    发明申请
    FOLDED MEMORY MODULES 有权

    公开(公告)号：US20210124703A1

    公开(公告)日：2021-04-29

    申请号：US16950861

    申请日：2020-11-17

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    LOAD REDUCED MEMORY MODULE
    7.
    发明申请
    LOAD REDUCED MEMORY MODULE 有权

    公开(公告)号：US20210120669A1

    公开(公告)日：2021-04-22

    申请号：US17072775

    申请日：2020-10-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan

    IPC: H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F1/18 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40

    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
    8.
    发明申请
    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 审中-公开

    公开(公告)号：US20190266112A1

    公开(公告)日：2019-08-29

    申请号：US16290346

    申请日：2019-03-01

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

    IPC: G06F13/16 ,  G06F13/00 ,  G06F13/42

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    Memory repair using external tags
    9.
    发明授权
    Memory repair using external tags 有权

    公开(公告)号：US09734921B2

    公开(公告)日：2017-08-15

    申请号：US14407318

    申请日：2013-10-31

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ian Shaeffer

    IPC: G11C29/44 ,  G11C29/00 ,  G06F11/10

    CPC classification number: G11C29/4401 ,  G06F11/1016 ,  G06F11/1072 ,  G11C29/808 ,  G11C29/846

    Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.

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