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    System and method for signature-based systematic condition detection and analysis
    1.
    发明授权
    System and method for signature-based systematic condition detection and analysis 失效
    基于签名的系统状态检测和分析的系统和方法

    公开(公告)号：US07853848B2

    公开(公告)日：2010-12-14

    申请号：US11875975

    申请日：2007-10-22

    申请人： Rao H. Desineni ,  Maroun Kassab ,  Leah M. Pastel

    发明人： Rao H. Desineni ,  Maroun Kassab ,  Leah M. Pastel

    IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/26 ,  G01R31/08 ,  G06F17/50

    CPC分类号： G01R31/318321

    摘要： Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

    摘要翻译： 公开了用于检测和分析在制造的装置中发生的系统状况的系统，方法和服务的实施例。 每个实施例包括为多个被测试设备中的每一个产生唯一的签名。 基于签名定义的初始集合以及至少部分地从选定的测试数据导出的那些签名定义的值来生成签名。 基于签名之间的共同点检测系统条件。 然后单独或与附加信息一起分析系统条件，以便开发设备之间的基本相似性列表。 分析结果可用于通过修改签名定义集和/或通过修改数据选择来完善系统状态检测和分析过程。

    SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS
    2.
    发明申请
    SYSTEM AND METHOD FOR SIGNATURE-BASED SYSTEMATIC CONDITION DETECTION AND ANALYSIS 失效
    用于基于签名的系统状态检测和分析的系统和方法

    公开(公告)号：US20090106614A1

    公开(公告)日：2009-04-23

    申请号：US11875975

    申请日：2007-10-22

    申请人： Rao H. Desineni ,  Maroun Kassab ,  Leah M. Pastel

    发明人： Rao H. Desineni ,  Maroun Kassab ,  Leah M. Pastel

    IPC分类号： G01R31/3181 ,  G06F11/26

    CPC分类号： G01R31/318321

    摘要： Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

    摘要翻译： 公开了用于检测和分析在制造的装置中发生的系统状况的系统，方法和服务的实施例。 每个实施例包括为多个被测试设备中的每一个产生唯一的签名。 基于签名定义的初始集合以及至少部分地从选定的测试数据导出的那些签名定义的值来生成签名。 基于签名之间的共同点检测系统条件。 然后单独或与附加信息一起分析系统条件，以便开发设备之间的基本相似性列表。 分析结果可用于通过修改签名定义集和/或通过修改数据选择来完善系统状态检测和分析过程。

    INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION
    3.
    发明申请
    INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION 失效
    在模拟中使用的逻辑模型中的故障插入

    公开(公告)号：US20110137602A1

    公开(公告)日：2011-06-09

    申请号：US12633151

    申请日：2009-12-08

    申请人： Rao H. Desineni ,  Maroun Kassab ,  Mary P. Kusko ,  Leah M. Pastel

    发明人： Rao H. Desineni ,  Maroun Kassab ,  Mary P. Kusko ,  Leah M. Pastel

    IPC分类号： G01R31/14 ,  G06F17/50

    CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F2217/70

    摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.

    摘要翻译： 一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则 满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。

    Insertion of faults in logic model used in simulation
    4.
    发明授权
    Insertion of faults in logic model used in simulation 失效
    在模拟中使用的逻辑模型中插入故障

    公开(公告)号：US08566059B2

    公开(公告)日：2013-10-22

    申请号：US12633151

    申请日：2009-12-08

    申请人： Rao H. Desineni ,  Maroun Kassab ,  Mary P. Kusko ,  Leah M. Pastel

    发明人： Rao H. Desineni ,  Maroun Kassab ,  Mary P. Kusko ,  Leah M. Pastel

    IPC分类号： G06F17/50 ,  G01R31/00

    CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F2217/70

    摘要： A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.

    摘要翻译： 一种基于集成电路（IC）布局的物理布局选择故障候选的方法，其包括：识别IC布局中的故障观察点，确定IC电路布局中的故障观察点接近度几何，确定接近度准则 满足故障观测点，识别符合接近度标准的故障观测点相关故障; 并在故障候选集中包括识别的故障。

    Identifying defects
    5.
    发明授权
    Identifying defects 有权
    识别缺陷

    公开(公告)号：US08571299B2

    公开(公告)日：2013-10-29

    申请号：US12871039

    申请日：2010-08-30

    申请人： Mohammed F. Fayaz ,  Julie L. Lee ,  Leah M. Pastel ,  Maroun Kassab

    发明人： Mohammed F. Fayaz ,  Julie L. Lee ,  Leah M. Pastel ,  Maroun Kassab

    IPC分类号： G06K9/00

    CPC分类号： G01N21/95607 ,  G01N2021/8864 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

    摘要翻译： 识别晶片处理中的系统缺陷，包括执行多个晶片的缺陷检查，将多个晶片中的每一个中的缺陷识别为不与平凡和/或已知的根本原因相关联，确定每个晶片上的每个晶片上的物理位置 发生缺陷，并将每个缺陷发生的物理位置与为这些物理位置定义的单元格实例相关联。

    IDENTIFYING DEFECTS
    6.
    发明申请
    IDENTIFYING DEFECTS 有权
    识别缺陷

    公开(公告)号：US20120050728A1

    公开(公告)日：2012-03-01

    申请号：US12871039

    申请日：2010-08-30

    申请人： Mohammed F. Fayaz ,  Maroun Kassab ,  Julie L. Lee ,  Leah M. Pastel

    发明人： Mohammed F. Fayaz ,  Maroun Kassab ,  Julie L. Lee ,  Leah M. Pastel

    IPC分类号： G01N21/00 ,  G06F19/00

    CPC分类号： G01N21/95607 ,  G01N2021/8864 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

    摘要翻译： 识别晶片处理中的系统缺陷，包括执行多个晶片的缺陷检查，将多个晶片中的每一个中的缺陷识别为不与平凡和/或已知的根本原因相关联，确定每个晶片上的每个晶片上的物理位置 发生缺陷，并将每个缺陷发生的物理位置与为这些物理位置定义的单元格实例相关联。

    Sensor differentiated fault isolation
    7.
    发明授权
    Sensor differentiated fault isolation 有权
    传感器差分故障隔离

    公开(公告)号：US07397263B2

    公开(公告)日：2008-07-08

    申请号：US11670001

    申请日：2007-02-01

    申请人： Kevin L. Condon ,  Theodore M. Levin ,  Leah M. Pastel ,  David P. Vallett

    发明人： Kevin L. Condon ,  Theodore M. Levin ,  Leah M. Pastel ,  David P. Vallett

    IPC分类号： G01R31/02

    CPC分类号： G01R31/311 ,  G01R31/302 ,  G01R31/31728 ,  G01R31/3187

    摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.

    摘要翻译： 公开了一种用于诊断测试设备内的电路的装置和方法。 该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个 响应。 本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。 相关器被配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性 能源的位置和传感器的位置。

    METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING
    9.
    发明申请
    METHODS FOR DESIGNING A PRODUCT CHIP A PRIORI FOR DESIGN SUBSETTING, FEATURE ANALYSIS, AND YIELD LEARNING 有权
    设计产品芯片的设计方法，设计分析，特征分析和理论学习

    公开(公告)号：US20090259983A1

    公开(公告)日：2009-10-15

    申请号：US12103217

    申请日：2008-04-15

    申请人： John M. Cohn ,  Leah M. Pastel ,  Gustavo E. Tellez

    发明人： John M. Cohn ,  Leah M. Pastel ,  Gustavo E. Tellez

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plurality of signal paths that have physical design constraints to generate a subset of the plurality of signal paths. The method further includes constructing a physical implementation of each of the signal paths in the subset, identifying one or more signal paths in the subset that are not constructed consistently with the respective physical implementation, and removing those signal paths from the subset.

    摘要翻译： 一种用于设计子集，特征分析和产量学习的芯片设计方法。 该方法包括识别可以从芯片故障数据容易地识别的芯片设计中的多个信号路径，并且去除具有物理设计约束以生成多个信号路径的子集的多个信号路径的一部分。 该方法还包括构建子集中的每个信号路径的物理实现，识别子集中未与相应物理实现一致构造的一个或多个信号路径，以及从该子集中去除那些信号路径。