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公开(公告)号：US5584009A
公开(公告)日：1996-12-10
申请号：US138654
申请日：1993-10-18
CPC分类号： G06F9/30043 , G06F12/0855 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F12/04
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写入缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。
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公开(公告)号：US5907860A
公开(公告)日：1999-05-25
申请号：US688900
申请日：1996-07-31
CPC分类号： G06F9/30043 , G06F12/0855 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F12/04
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes). are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 用于处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。 也被披露。
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公开(公告)号：US5835949A
公开(公告)日：1998-11-10
申请号：US831842
申请日：1997-04-02
IPC分类号： G06F9/38
CPC分类号： G06F9/3812
摘要： A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction cache from which the instructions originate.
摘要翻译： 公开了一种在流水线处理器中容易地识别和处理自修改可变长度指令的系统和方法，其采用与执行流水线的每个级相关联的索引标签，其中索引标签识别指令来自的指令高速缓存中的高速缓存行数 。
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公开(公告)号：US5963984A
公开(公告)日：1999-10-05
申请号：US857300
申请日：1997-05-16
CPC分类号： G06F12/1027 , G06F2212/651 , G06F2212/652 , G06F2212/681
摘要： Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside buffers. Selective comparisons between contents on a linear address bus and linear address tags are controlled by a size mask register which further controls a multiplexer to selectively steer bits onto a physical address bus from either the linear address bus or a physical address register.
摘要翻译： 公开了用于虚拟寻址的系统和方法，其具有通过采用直接的，受害的和可编程的块翻译放置缓冲器的具有可变页面大小的地址转换单元。 线性地址总线和线性地址标签上的内容之间的选择性比较由大小屏蔽寄存器控制，该大小屏蔽寄存器进一步控制多路复用器以选择性地将位从线性地址总线或物理地址寄存器转向物理地址总线。
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公开(公告)号：US5752274A
公开(公告)日：1998-05-12
申请号：US336030
申请日：1994-11-08
CPC分类号： G06F12/1027 , G06F2212/681
摘要： An address translation unit is disclosed employing a direct-mapped translation lookaside buffer and a relatively small, associative victim translation lookaside buffer for translating linear addresses to physical addresses expediently and avoiding thrashing, without requiring large amounts of hardware and space.
摘要翻译： 公开了一种地址翻译单元，其使用直接映射翻译后备缓冲器和相对较小的关联受害者转换后备缓冲器，用于将线性地址有利地翻译为物理地址，并避免颠覆，而不需要大量的硬件和空间。
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6.发明授权Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch 失效具有识别地址是否属于第一写操作数的信息的统一写缓冲器或具有额外宽锁存器的第二写操作数
公开(公告)号：US5615402A
公开(公告)日：1997-03-25
申请号：US572584
申请日：1995-12-14
CPC分类号： G06F9/30043 , G06F12/0855 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F12/04
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写入缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。
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7.发明授权System and method of retiring misaligned write operands from a write buffer 失效从写缓冲区中退出未对齐的写操作数的系统和方法公开(公告)号：US06219773B1
公开(公告)日：2001-04-17
申请号：US08138790
申请日：1993-10-18
IPC分类号： G06F1204
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F12/04 , G06F12/0855
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads form memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写入缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 写入缓冲区中的数据写入也以程序顺序排列，因此存储器的非可缓存读取也被排序。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。
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8.发明授权Data dependency detection and handling in a microprocessor with write buffer 失效具有写入缓冲器的微处理器中的数据依赖性检测和处理
公开(公告)号：US5471598A
公开(公告)日：1995-11-28
申请号：US139596
申请日：1993-10-18
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3863 , G06F9/3865 , G06F9/3875
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。
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9.发明授权Error detecting method and apparatus for computer memory having multi-bit output memory circuits 失效具有多位输出存储电路的计算机存储器的误差检测方法和装置
公开(公告)号：US5291498A
公开(公告)日：1994-03-01
申请号：US647408
申请日：1991-01-29
CPC分类号： G06F11/1028 , G06F11/102
摘要： An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or parity bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome. The check bit syndrome is decoded to produce an output that is input to an error generator circuit together with a parity syndrome for producing error signals indicating occurrence of a single bit error, a multi-bit error, a triple bit error, or a check bit error.
摘要翻译： 错误校正码和装置与主存储器一起使用，其中数据字存储在多个电路中，每个电路产生多个输出。 最小数量的校验位与数据字一起存储，用于检测和校正单个位错误并检测多位错误的存在。 整个数据字的奇偶校验位也被存储。 对于32位数据字，数据字的至少3位存储在10个存储器电路的每一个中。 七个校验位和一个奇偶校验位也存储在10个存储器电路中，其中校验位或奇偶校验位中不超过一个存储在任何一个存储器电路中。 在从存储器读取数据字时，生成一组验证校验位和验证奇偶校验位，并与存储的校验位和存储的校验位进行比较以产生校验位综合征和奇偶校验位综合征。 校验位校验码被解码以产生输出，其输出到错误发生器电路以及用于产生指示出现单个位错误，多位错误，三位误差或校验位的错误信号的奇偶校验 错误。
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10.发明授权
公开(公告)号：US5740398A
公开(公告)日：1998-04-14
申请号：US138651
申请日：1993-10-18
申请人： Marc A. Quattromani , Nital Patwa
发明人： Marc A. Quattromani , Nital Patwa
CPC分类号： G06F9/30043 , G06F12/0855 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3842 , G06F9/3865 , G06F12/04
摘要： A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.
摘要翻译： 公开了一种具有位于核心和高速缓存之间的写缓冲器的超标量超管道微处理器。 控制写入缓冲器以将写入操作的结果存储到存储器，直到缓存变得可用的时间，例如当不执行高优先级读取时。 写缓冲器包括被分成两个循环缓冲区段的多个条目，以便于与核心的两个管线的交互; 为每个写入缓冲区条目提供交叉依赖关系表，以确保以相应部分存在先前数据的可能性，以数据顺序将写入缓冲区写入存储器。 来自存储器的不可缓存读取也按照程序顺序排序，并从写入缓冲区写入数据。 还公开了处理推测执行，检测和处理数据依赖关系和异常以及执行特殊写入功能（未对齐写入和收集的写入）的功能。
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