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1.发明授权Physical interface macros (PHYS) supporting heterogeneous electrical properties 失效物理接口宏（PHYS）支持异质电气特性公开(公告)号：US08051228B2
公开(公告)日：2011-11-01
申请号：US12270576
申请日：2008-11-13
CPC分类号： G06F13/4022 , G06F13/4072 , G06F2213/0026 , G06F2213/0028 , Y02D10/14 , Y02D10/151
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。
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2.发明申请Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip 有权在单芯片上支持多个高带宽I / O控制器的方法和装置公开(公告)号：US20100122011A1
公开(公告)日：2010-05-13
申请号：US12270569
申请日：2008-11-13
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。
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3.发明申请Physical Interface Macros (PHYS) Supporting Heterogeneous Electrical Properties 失效物理接口宏（PHYS）支持异构电气特性公开(公告)号：US20100122107A1
公开(公告)日：2010-05-13
申请号：US12270576
申请日：2008-11-13
CPC分类号： G06F13/4022 , G06F13/4072 , G06F2213/0026 , G06F2213/0028 , Y02D10/14 , Y02D10/151
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。
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4.发明授权公开(公告)号：US08332552B2
公开(公告)日：2012-12-11
申请号：US12270569
申请日：2008-11-13
IPC分类号： G06F3/00 , G06F13/12 , G06F13/00 , G06F13/42 , G06F15/76 , G06F9/44 , H04L12/28 , H04L12/50 , H03K19/173 , H01L25/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译： 集成处理器设计包括支持异质电气特性的物理接口宏。 处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或 串行连接SCSI（SAS）接口进行存储。 每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。 多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。 因此，物理接口宏可以以编程方式连接到多个控制器的子集。
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公开(公告)号：US07900016B2
公开(公告)日：2011-03-01
申请号：US12024744
申请日：2008-02-01
IPC分类号： G06F12/10
CPC分类号： G06F13/387 , H04L61/2007 , H04L61/35
摘要： An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.
摘要翻译： 提供了一种寻址模式，其中所有资源（包括存储器和设备）都使用互联网协议（IP）地址进行寻址。 任务（例如应用程序）可以分配一个IP地址范围而不是有效的地址范围。 因此，例如，诸如I / O适配器或甚至打印机的处理元件也可以使用IP地址来寻址，而不需要库调用，设备驱动器，固定存储器等。 该寻址模型还可以跨IP互连提供资源的完全虚拟化，从而允许进程通过网络访问I / O设备。
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公开(公告)号：US20090198837A1
公开(公告)日：2009-08-06
申请号：US12024695
申请日：2008-02-01
IPC分类号： G06F3/00
CPC分类号： G06F9/45558 , G06F2009/45579
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.
摘要翻译： 提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。 为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于 例。 异构处理元件模型抽象出I / O设备，使得针对I / O设备的通信可以被分组并通过网络发送。 因此，虚拟化平台可以打包用于远程位置的I / O设备的通信，并且在一定距离上发送分组化的通信，而不是必须对库进行呼叫，调用设备驱动器，引脚存储器等。
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7.发明申请Full Virtualization of Resources Across an IP Interconnect Using Page Frame Table 失效通过IP帧互连使用页面框架完整的资源虚拟化公开(公告)号：US20090198953A1
公开(公告)日：2009-08-06
申请号：US12024773
申请日：2008-02-01
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/1081 , H04L29/12018 , H04L61/10
摘要： An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.
摘要翻译： 提供了一种寻址模型，其中包括I / O设备在内的设备通过互联网协议（IP）地址进行寻址，这些地址被认为是虚拟地址空间的一部分。 可以为任务（例如应用程序）分配与虚拟地址空间中的地址对应的有效地址范围。 虚拟地址空间被扩展为包括互联网协议地址。 因此，页框表也被修改为包括用于设备和I / O的IP地址和附加属性的条目。 因此，例如，诸如I / O适配器或甚至打印机的处理元件也可以使用IP地址来寻址，而不需要库调用，设备驱动器，固定存储器等。 该寻址模型还可以跨IP互连提供资源的完全虚拟化，从而允许进程通过网络访问I / O设备。
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8.发明申请Method for Data Processing Using a Multi-Tiered Full-Graph Interconnect Architecture 失效使用多层全图互连架构的数据处理方法公开(公告)号：US20090064139A1
公开(公告)日：2009-03-05
申请号：US11845207
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5061 , G06F2209/5012
摘要： A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
摘要翻译： 提供了一种实现多层全图互连架构的方法。 为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。 多个处理器书联接在一起以创建多个超节点。 然后，将多个超节点耦合在一起以创建多层全图互连体系结构。 然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。
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9.发明申请System for Data Processing Using a Multi-Tiered Full-Graph Interconnect Architecture 失效使用多层全图互连架构进行数据处理的系统公开(公告)号：US20090063811A1
公开(公告)日：2009-03-05
申请号：US11845206
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
IPC分类号： G06F15/80
CPC分类号： G06F15/16
摘要： A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
摘要翻译： 提供了一种用于实现多层全图互连体系结构的系统。 为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。 多个处理器书联接在一起以创建多个超节点。 然后，将多个超节点耦合在一起以创建多层全图互连体系结构。 然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。
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公开(公告)号：US09811097B2
公开(公告)日：2017-11-07
申请号：US12425210
申请日：2009-04-16
CPC分类号： G05D23/1931
摘要： A system and computer program product are provided for controlling liquid-cooled electronics, which includes measuring a first set point temperature, Ta, wherein the Ta is based on a dew point temperature, Tdp of a computer room. A second set point temperature, Tb, is measured, wherein the Tb is based on a facility chilled liquid inlet temperature, Tci, and a rack power, Prack, of an electronics rack. A Modular Cooling Unit (MCU) set point temperature, Tsp, is selected. The Tsp is the higher value of said Ta and said Tb. Responsive to the selected Tsp, a control valve is regulated. The control valve controls a flow of liquid that passes through a heat exchanger.
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