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公开(公告)号：US20110239069A1
公开(公告)日：2011-09-29
申请号：US12729826
申请日：2010-03-23
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G06F11/267 , G01R31/318541 , G01R31/318575
摘要： A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
摘要翻译： 具有测试扫描的数字扫描链系统具有多个触发器模块，多个触发器模块中的每一个具有第一数据位输入，第二数据位输入，测试位输入，时钟输入，第一 数据位输出，第二数据位输出和测试位输出。 第一触发器模块的测试位输出直接连接到第二触发器模块的测试位输入，而没有中间电路。 第一和第二复用主/从触发器直接串行连接。 时钟锁存器耦合到第二复用主/从触发器的输出并提供测试位输出。 时钟锁存器仅在测试模式下计时才能节省电量。
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公开(公告)号：US08484523B2
公开(公告)日：2013-07-09
申请号：US12729826
申请日：2010-03-23
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/318541 , G01R31/318575
摘要： A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
摘要翻译： 具有测试扫描的数字扫描链系统具有多个触发器模块，多个触发器模块中的每一个具有第一数据位输入，第二数据位输入，测试位输入，时钟输入，第一 数据位输出，第二数据位输出和测试位输出。 第一触发器模块的测试位输出直接连接到第二触发器模块的测试位输入，而没有中间电路。 第一和第二复用主/从触发器直接串行连接。 时钟锁存器耦合到第二复用主/从触发器的输出并提供测试位输出。 时钟锁存器仅在测试模式下计时才能节省电量。
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公开(公告)号：US20110095800A1
公开(公告)日：2011-04-28
申请号：US12607574
申请日：2009-10-28
CPC分类号： H03K3/356156 , H03K3/356173
摘要： A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.
摘要翻译： 一种操作电路的方法包括在第一节点处接收第一数据信号。 第一节点耦合到第二节点以将第一数据信号耦合到第二节点。 在将第一节点耦合到第二节点之后，第二节点耦合到第三节点以将第一数据信号耦合到第三节点。 执行第一节点与第二节点的耦合，并且执行在第三节点处锁存第一数据信号的第一步骤，其中锁定的第一步骤是通过第二节点，而第二节点耦合到第三节点。 第二节点与第三节点分离，并执行锁定的第二步骤，其中第一数据信号在第三节点处锁存，而第二节点与第三节点分离。
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4.发明授权公开(公告)号：US07623404B2
公开(公告)日：2009-11-24
申请号：US11561449
申请日：2006-11-20
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C7/1072 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/16 , G11C11/412
摘要： A memory device includes a latch having an input to receive a bit value, an input to receive a clock signal, and an output to provide a latched bit value based on the clock signal. The memory device further includes a bit cell including a storage component, and a write row driver configured to enable write access to the bit cell to store the latched bit value at the storage component for a first phase and a second phase of a cycle of the clock signal, the second phase following the first phase, and a read row driver configured to disable read access to the bit cell for the first phase of the cycle of the clock signal and to enable read access to the bit cell for the second phase of the cycle of the clock signal.
摘要翻译： 存储器件包括具有用于接收位值的输入端的锁存器，用于接收时钟信号的输入端以及基于时钟信号提供锁存位值的输出端。 存储器件还包括一个包含一个存储器件的位单元和一个写入行驱动器，该写入行驱动器被配置为使得能够对该位单元进行写访问，以便将该锁存位值存储在存储元件处，用于存储元件的第一阶段和第二阶段 时钟信号，第一阶段之后的第二阶段，以及读行驱动器，被配置为禁止对时钟信号的周期的第一阶段的位单元的读取访问，并且使得能够读取对位单元的第二阶段 时钟信号的周期。
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公开(公告)号：US07200020B2
公开(公告)日：2007-04-03
申请号：US11215655
申请日：2005-08-30
IPC分类号： G11C15/00
CPC分类号： G11C7/20
摘要： A storage device and a method in the storage element, where the storage element has a first data storage node and a second data storage node and where the first data storage node is coupled to a bit line via a first pass transistor and where the second data storage node is coupled to a complementary bit line via a second pass transistor, is provided. The method includes performing a clear operation on the first data storage node and the second data storage node by providing a clear signal to a first clear transistor coupled to the first data storage node and a second clear transistor coupled to the second data storage node.
摘要翻译： 存储装置和存储元件中的方法，其中所述存储元件具有第一数据存储节点和第二数据存储节点，并且其中所述第一数据存储节点经由第一传输晶体管耦合到位线，并且其中所述第二数据 存储节点通过第二传输晶体管耦合到互补位线。 该方法包括通过向耦合到第一数据存储节点的第一清除晶体管提供清除信号，以及耦合到第二数据存储节点的第二透明晶体管，对第一数据存储节点和第二数据存储节点执行清除操作。
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公开(公告)号：US20130046928A1
公开(公告)日：2013-02-21
申请号：US13213900
申请日：2011-08-19
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译： 一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126） 不使用操作数加法器的输出和从操作数（111,113）中读出。 将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。 从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。
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公开(公告)号：US08143929B2
公开(公告)日：2012-03-27
申请号：US12607574
申请日：2009-10-28
IPC分类号： H03K3/356
CPC分类号： H03K3/356156 , H03K3/356173
摘要： A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, the second node is coupled to a third node to couple the first data signal to the third node. The first node is decoupled from the second node and a first step of latching the first data signal at the third node is performed, wherein the first step of latching is through the second node while the second node is coupled to the third node. The second node is decoupled from the third node and a second step of latching is performed wherein the first data signal latched at the third node while the second node is decoupled from the third node.
摘要翻译： 一种操作电路的方法包括在第一节点处接收第一数据信号。 第一节点耦合到第二节点以将第一数据信号耦合到第二节点。 在将第一节点耦合到第二节点之后，第二节点耦合到第三节点以将第一数据信号耦合到第三节点。 执行第一节点与第二节点的耦合，并且执行在第三节点处锁存第一数据信号的第一步骤，其中锁定的第一步骤是通过第二节点，而第二节点耦合到第三节点。 第二节点与第三节点分离，并执行锁定的第二步骤，其中第一数据信号在第三节点处锁存，而第二节点与第三节点分离。
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8.发明申请公开(公告)号：US20080198681A1
公开(公告)日：2008-08-21
申请号：US11676341
申请日：2007-02-19
IPC分类号： G11C8/16
摘要： A multiple port memory has a word line driver that provides a word line signal to access a first write port of a multiple port memory cell in an array of multiple port memory cells during a write operation. A first logic circuit has a first input for receiving a first port selection signal, a second input for receiving a disable signal, and an output. A buffer circuit has an input coupled to the output of the first logic circuit, and an output for providing the word line signal. The disable signal is asserted to prevent the word line driver from accessing the first write port when a second write port of the multiple port memory cell is accessed during the write operation and the second write port has a higher priority than the first write port.
摘要翻译： 多端口存储器具有字线驱动器，其在写操作期间提供字线信号以访问多端口存储器单元阵列中的多端口存储器单元的第一写端口。 第一逻辑电路具有用于接收第一端口选择信号的第一输入端，用于接收禁止信号的第二输入端和输出端。 缓冲电路具有耦合到第一逻辑电路的输出的输入和用于提供字线信号的输出。 当在写入操作期间访问多端口存储器单元的第二写入端口并且第二写入端口具有比第一写入端口更高的优先级时，禁止信号被断言以防止字线驱动器访问第一写入端口。
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公开(公告)号：US20080054943A1
公开(公告)日：2008-03-06
申请号：US11470342
申请日：2006-09-06
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/20
摘要： A variable switching point inverter (30) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (VIN) by changing the P/N ratio of the inverter based on the delayed output state (VOUT) of the inverter. The variable switching point inverter may be constructed as a CMOS integrated circuit with a first inverter stage (33, 34) coupled in parallel to a second inverter stage (35, 36) having extra PMOS (37) and NMOS (38) transistors connected to VDD and VSS, respectively, where the extra PMOS and NMOS transistors are controlled by the delayed output signal (40) generated by a delay element (39) coupled to the output of the first inverter stage. By using a delayed feed back signal (40) to control the extra PMOS and NMOS gates (37, 38), the switching point voltage of the first inverter stage (33, 34) is altered, depending on whether the input transitions are high-to-low or low-to-high.
摘要翻译： 公开了一种可变开关点逆变器（30），其通过基于延迟输出来改变逆变器的P / N比来降低上升沿和下降沿输入电压（V IN IN）降低的阈值电压 状态（V OUT OUT）。 可变开关点反相器可以被构造为具有与具有额外的PMOS（37）和NMOS（38）晶体管的第二反相器级（35,36）并联耦合的第一反相器级（33,34）的CMOS集成电路，所述第二反相器级连接到 其中分压PMOS和NMOS晶体管由延迟输出信号（40）控制，延迟输出信号（40）由耦合到该延迟元件（39）的延迟元件（39）产生， 输出第一个反相器级。 通过使用延迟反馈信号（40）来控制额外的PMOS和NMOS栅极（37,38），根据输入转换是否为高电平，第一反相器级（33,34）的开关点电压被改变， 从低到高还是从低到高。
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公开(公告)号：US09021194B2
公开(公告)日：2015-04-28
申请号：US13213900
申请日：2011-08-19
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译： 一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126） 不使用操作数加法器的输出和从操作数（111,113）中读出。 将来自操作数（111,113）的PGZ编码的地址位（0:51）与进位值（Cout48）一起施加到内容寻址存储器阵列（114），以产生两个推测的命中/未命中信号。 从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。
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