公开(公告)号：US10998020B1

公开(公告)日：2021-05-04

申请号：US16866886

申请日：2020-05-05

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Fu-Chin Tsai ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Gerchih Chou ,  Kuo-Wei Chi ,  Shih-Chang Chen ,  Shih-Han Lin ,  Min-Han Tsai

IPC分类号： G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  H03K7/08 ,  G11C8/18

摘要： The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

公开(公告)号：US10978118B1

公开(公告)日：2021-04-13

申请号：US16682689

申请日：2019-11-13

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Chun-Chi Yu ,  Fu-Chin Tsai ,  Chih-Wei Chang ,  Gerchih Chou

IPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C7/04 ,  G11C11/4093 ,  G06F3/06

摘要： Disclosed is a DDR SDRAM signal calibration device capable to adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal pad configured to output a DQS signal; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and the DQS signal; and a calibration circuit configured to output a calibration signal according to the DQS enablement setting signal and at least one of the DQS enablement signal and the DQS signal so that the enablement signal setting circuit can maintain or adjust the DQS enablement setting according to the calibration signal.

公开(公告)号：US10741231B1

公开(公告)日：2020-08-11

申请号：US16408873

申请日：2019-05-10

申请人： Realtek Semiconductor Corporation

发明人： Fu-Chin Tsai ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Gerchih Chou

IPC分类号： G11C8/18 ,  G11C16/08 ,  G06F1/08 ,  H03L7/07 ,  G06F1/12 ,  G11C16/32

摘要： A memory access interface device that includes a clock generation circuit that generates reference clock signals according to a source clock signal and access signal transmission circuits are provided. Each of the access signal transmission circuits includes a first and a second clock frequency division circuits, a phase adjusting circuit and a duty cycle adjusting circuit. The first and the second clock frequency division circuits sequentially divide the frequency of one of the reference clock signals to generate a first and a second frequency divided clock signals respectively. The phase adjusting circuit adjusts the phase of an access signal according to the second frequency divided clock signal to generate a phase-adjusted access signal. The duty cycle adjusting circuit adjusts the duty cycle of the phase-adjusted access signal to be a half of the time period to generate an output access signal to access a memory device.

公开(公告)号：US09135980B2

公开(公告)日：2015-09-15

申请号：US14326869

申请日：2014-07-09

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Chun-Chi Yu ,  Chih-Wei Chang ,  Shen-Kuo Huang

IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/4091 ,  G11C7/10

CPC分类号： G11C11/4076 ,  G06F13/1689 ,  G11C7/1057 ,  G11C7/1066 ,  G11C11/4091

摘要： This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.

摘要翻译： 本发明公开了一种存储器控制电路和控制存储器模块的数据读取过程的方法。 在数据读取处理中，存储器模块发送用于恢复数据信号的数据信号和数据选通信号。 数据选通信号包括前导码部分。 该方法包括以下步骤：控制存储器模块的阻抗匹配电路，使得数据选通信号在前同步码部分之前保持在固定电平; 产生时钟; 根据时钟产生使能信号; 根据使能信号对数据选通信号进行采样，生成采样结果; 根据采样结果调整使能信号的使能时间; 并根据使能信号开始数据信号的数据恢复处理。

公开(公告)号：US12009056B2

公开(公告)日：2024-06-11

申请号：US17861424

申请日：2022-07-11

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Fu-Chin Tsai ,  Ger-Chih Chou ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Shih-Han Lin

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/222 ,  G11C7/1012 ,  G11C7/109

摘要： The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least ┌P┐.

公开(公告)号：US11978497B2

公开(公告)日：2024-05-07

申请号：US17528208

申请日：2021-11-17

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Kuo-Wei Chi ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Ger-Chih Chou

IPC分类号： G11C7/22 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/50

CPC分类号： G11C11/4076 ,  G06F3/0644 ,  G11C7/1078 ,  G11C7/222 ,  G11C11/4093 ,  G11C29/50012 ,  G11C2207/2254

摘要： Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.

公开(公告)号：US09570130B2

公开(公告)日：2017-02-14

申请号：US15093758

申请日：2016-04-08

申请人： Realtek Semiconductor Corporation

发明人： Chun-Chi Yu ,  Chih-Wei Chang ,  Gerchih Chou ,  Fu-Chin Tsai ,  Shih-Chang Chen

IPC分类号： G11C7/22

CPC分类号： G11C7/222 ,  G11C7/22

摘要： A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.

摘要翻译： 提供电连接在存储器控制器和存储器件之间的存储器物理层接口电路。 存储器物理层接口电路包括坞站生成模块和先进先出（FIFO）模块。 时钟产生模块产生参考时钟信号并输出​​相关的时钟信号。 参考时钟信号被发送到存储器件。 每个FIFO模块根据写相关的时钟信号将存储器控制器发送的输入信息写入其中，并根据输出相关时钟信号之一检索输入信息，以产生输出信号。 输出信号被传送到存储器件以操作存储器件。 写相关时钟信号是通过除去输出相关时钟信号之一的频率而产生的。

公开(公告)号：US10522204B1

公开(公告)日：2019-12-31

申请号：US16183348

申请日：2018-11-07

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： Chun-Chi Yu ,  Fu-Chin Tsai ,  Shih-Han Lin ,  Chih-Wei Chang ,  Gerchih Chou

IPC分类号： G11C7/22 ,  G06F3/06

摘要： A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.

公开(公告)号：US12088359B2

公开(公告)日：2024-09-10

申请号：US17938050

申请日：2022-10-05

申请人： Realtek Semiconductor Corporation

发明人： Shih-Chang Chen ,  Chih-Wei Chang ,  Chun-Chi Yu

IPC分类号： H04B17/345

CPC分类号： H04B17/345

摘要： An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.

公开(公告)号：US11055255B2

公开(公告)日：2021-07-06

申请号：US16741932

申请日：2020-01-14

申请人： Realtek Semiconductor Corporation

发明人： Fu-Ching Hsu ,  Chih-Wei Chang

IPC分类号： G06F13/40 ,  G06F13/38 ,  G06F13/42

摘要： An interface connection apparatus disposed in a first electronic device is provided that includes an analog physical layer circuit, a waveform generation circuit and a media access control circuit. The analog physical layer circuit receives an analog handshake signal from a second electronic device and generates a digital handshake signal. The waveform generation circuit determines whether a matching times that a pulse parameter of each of pulses included in the digital handshake signal is within a predetermined pulse parameter range reaches predetermine times and generates a digital output signal when the matching times reaches the predetermine times, and an output pulse parameter of all output pulses of the digital output signal is within the predetermined pulse parameter range. The media access control circuit determines that the analog handshake signal is valid when the media access control circuit receives the digital output signal to keep performing handshake.