公开(公告)号：US20210333233A1

公开(公告)日：2021-10-28

申请号：US16858320

申请日：2020-04-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro SHIRAI

IPC: G01N27/414

Abstract: A semiconductor device includes a first terminal receiving a first signal, a second terminal receiving a second signal, a noise extraction analysis unit extracting a signal of a specific frequency component from the first and the second signal, a feedback unit generating a feedback signal based on a magnitude of the signal of the specific frequency component to cancel the signal of the specific frequency component superimposed on the first and the second signal, and third terminal outputting to the feedback signal to outside.

公开(公告)号：US20190298189A1

公开(公告)日：2019-10-03

申请号：US16286410

申请日：2019-02-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro SHIRAI

IPC: A61B5/021 ,  G01H5/00 ,  G01H11/08 ,  A61B5/00

Abstract: A measuring device and measuring system which accurately measure a pulse wave propagation velocity. The measuring instrument includes: a fixing part attachable to and detachable from a subject; a first piezoelectric sensor fixed to the fixing part; a second piezoelectric sensor fixed to the fixing part at a prescribed distance from the first piezoelectric sensor; and an analyzing part for calculating a pulse wave propagation velocity in the subject according to time difference between time of detection of peak voltage by the first piezoelectric sensor and time of detection of peak voltage by the second piezoelectric sensor, and the prescribed distance.

公开(公告)号：US20170093325A1

公开(公告)日：2017-03-30

申请号：US15232176

申请日：2016-08-09

Applicant: Renesas Electronics Corporation

Inventor： Toshiya NOZAWA ,  Yoshitaro KONDO ,  Yusuke SUGAWARA ,  Shoichi KAMIMURA ,  Masatoshi MAEDA ,  Yasuhiro SHIRAI

IPC: H02P29/68 ,  H02P29/024

CPC classification number: H02P29/68 ,  H02M7/48 ,  H02P29/027

Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).

公开(公告)号：US20160049466A1

公开(公告)日：2016-02-18

申请号：US14826075

申请日：2015-08-13

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Akio ICHIMURA ,  Toshiaki IGARASHI ,  Yasuhiro SHIRAI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/045 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7827

Abstract: To improve characteristics of a semiconductor device (vertical power MOSFET). A spiral p-type column region having a corner is formed in a peripheral region surrounding a cell region in which a semiconductor element is formed. In an epitaxial layer of the peripheral region surrounding the cell region in which the semiconductor element is formed, a trench spirally surrounding the cell region and having the first and second side faces making up the corner is formed and the trench is filled with the epitaxial layer. By spirally arranging the p-type column region (n-type column region) in such a manner, a drop in a withstand voltage margin due to a hot spot can be avoided. In addition, the continuity of the p-type column region (n-type column region) is maintained. As a result, electric field concentration is alleviated step by step toward the outer periphery and the withstand voltage is therefore increased.

Abstract translation: 改善半导体器件（垂直功率MOSFET）的特性。 在围绕形成有半导体元件的单元区域的周边区域中形成具有角部的螺旋状p型列区域。 在围绕形成有半导体元件的单元区域的外围区域的外延层中，形成螺旋状包围单元区域并且具有构成拐角的第一和第二侧面的沟槽，并且沟槽被外延层填充 。 通过以这种方式螺旋地排列p型列区域（n型列区域），可以避免由于热点导致的耐受电压裕度的下降。 此外，保持p型列区域（n型列区域）的连续性。 结果，逐渐朝向外周逐渐减小电场浓度，耐压提高。

公开(公告)号：US20180048257A1

公开(公告)日：2018-02-15

申请号：US15791817

申请日：2017-10-24

Applicant: Renesas Electronics Corporation

Inventor： Toshiya NOZAWA ,  Yoshitaro KONDO ,  Yusuke SUGAWARA ,  Shoichi KAMIMURA ,  Masatoshi MAEDA ,  Yasuhiro SHIRAI

IPC: H02P29/68 ,  H02M7/48 ,  H02P29/024

CPC classification number: H02P29/68 ,  H02M7/48 ,  H02P29/027

Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).