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公开(公告)号：US20170248984A1
公开(公告)日：2017-08-31
申请号：US15597282
申请日：2017-05-17
Applicant: Renesas Electronics Corporation
Inventor： Atsushi MOTOZAWA , Yuichi OKUDA
IPC: G05F3/30
Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.
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Patent Agency Ranking
公开(公告)号：US20170250692A1
公开(公告)日：2017-08-31
申请号：US15441936
申请日：2017-02-24
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Atsushi MOTOZAWA , Yoshitaka HIRAI
CPC classification number: H03L7/0802 , H02M3/07 , H03K19/017509 , H03L7/087 , H03L7/099 , H03L7/0991 , H03L7/18 , H03M1/742
Abstract: An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.
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公开(公告)号：US20240072779A1
公开(公告)日：2024-02-29
申请号：US18364225
申请日：2023-08-02
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Atsushi MOTOZAWA
Abstract: A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.
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4.发明申请CURRENT GENERATION CIRCUIT, AND BANDGAP REFERENCE CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权电流产生电路，以及包括其的带状基准电路和半导体器件公开(公告)号：US20150293552A1
公开(公告)日：2015-10-15
申请号：US14669352
申请日：2015-03-26
Applicant: Renesas Electronics Corporation
Inventor： Atsushi MOTOZAWA , Yuichi OKUDA
IPC: G05F3/26
Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.
Abstract translation: 一种包括第一和第二双极晶体管的电流产生电路，使第一电流和第二电流分别通过第一和第二双极晶体管的电流分配电路分别对应于第一和第二双极晶体管的第一电流和第二电流 ，设置在所述第一双极晶体管和所述第一电流分配电路之间的第一NMOS晶体管，设置在所述第二双极晶体管和所述第一电流分配电路之间的第二NMOS晶体管，第一电阻元件，输出所述第二控制电压的第一运算放大器 根据第一NMOS晶体管的漏极电压和基准偏置电压到第一和第二NMOS晶体管的栅极;以及第二运算放大器，其根据第二NMOS晶体管的漏极电压和第二NMOS晶体管产生第一控制电压， 参考偏置电压。
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公开(公告)号：US20230387924A1
公开(公告)日：2023-11-30
申请号：US18307475
申请日：2023-04-26
Applicant: Renesas Electronics Corporation
Inventor： Yusuke IMANAKA , Atsushi MOTOZAWA
CPC classification number: H03L7/0998 , H03L7/1974
Abstract: A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.
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公开(公告)号：US20220131547A1
公开(公告)日：2022-04-28
申请号：US17501389
申请日：2021-10-14
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Atsushi MOTOZAWA
Abstract: A PLL circuit includes a phase comparator, an integrator path, a proportional path, a current controlled oscillator, a divider, and a double integrator path. The double integrator path includes an intermittent operation gm amplifier, a filter circuit, and a voltage-current conversion circuit. The intermittent operation gm amplifier receives an output voltage of a filter circuit. When a pulse CLK for an intermittent operation is ON, the intermittent operation gm amplifier outputs its voltage to the filter circuit. When the pulse CLK for the intermittent operation is OFF, the intermittent operation gm amplifier does not output the output voltage of the filter circuit to the filter circuit. Even when the pulse CLK for the intermittent operation is OFF, an input potential of the voltage-current conversion circuit is held by the filter circuit, and a current to the current controlled oscillator flows. This makes it possible to oscillate at a high frequency without increasing an area of the filter circuit.
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