公开(公告)号：US20180342577A1

公开(公告)日：2018-11-29

申请号：US15971130

申请日：2018-05-04

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII ,  Takahiro MORI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: A first comb portion of an n-type well region and a second comb portion of a p− drift region mesh with each other in plan view. A pn junction of the n-type well region and the p− drift region thus has a zigzag shape in plan view. The pn junction formed of the n-type well region and the p− drift region extends from a main surface toward a bottom surface of the isolation trench along a source-side wall surface of an isolation trench.

公开(公告)号：US20180102431A1

公开(公告)日：2018-04-12

申请号：US15837520

申请日：2017-12-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI ,  Hiroki FUJII

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/311 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

公开(公告)号：US20170179221A1

公开(公告)日：2017-06-22

申请号：US15381100

申请日：2016-12-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII

IPC: H01L29/06 ,  H01L27/06 ,  H01L23/522 ,  H03K17/687 ,  H01L23/532 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/823892 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/7816

Abstract: A semiconductor device according to one embodiment of the present invention comprises: a semiconductor substrate having a main surface; a noise source element formed at the main surface of the semiconductor substrate; a protection target element formed at the main surface of the semiconductor substrate; an n type region disposed between the noise source element and the protection target element; and a p type region disposed between the noise source element and the protection target element and electrically connected to the n type region. The n type region and the p type region are adjacent to each other on the main surface of the semiconductor substrate in a direction intersecting a direction from the noise source element toward the protection target element.

公开(公告)号：US20190067470A1

公开(公告)日：2019-02-28

申请号：US16036489

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII ,  Atsushi SAKAI ,  Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

公开(公告)号：US20180175192A1

公开(公告)日：2018-06-21

申请号：US15847342

申请日：2017-12-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki FUJII ,  Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0607 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p− drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p− drift region and directly below the recessed portion.

公开(公告)号：US20170287912A1

公开(公告)日：2017-10-05

申请号：US15463681

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Hiroki FUJII

IPC: H01L27/092 ,  H01L29/10 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/8249 ,  H01L23/528 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/1095

Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.

公开(公告)号：US20170025532A1

公开(公告)日：2017-01-26

申请号：US15172264

申请日：2016-06-03

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI ,  Hiroki FUJII

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/311 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor.In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

Abstract translation: 在具有横向MOS晶体管的半导体器件中，在位于漏区和栅电极之间的隔离绝缘膜的一部分处形成掩埋电极。 掩埋电极包括埋设部分。 掩埋部分由隔离绝缘膜的表面形成，直到与隔离绝缘膜的厚度相比较的深度。 掩埋电极电耦合到漏极区域。