公开(公告)号：US20230069864A1

公开(公告)日：2023-03-09

申请号：US17894579

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki MURAYAMA ,  Makoto KOSHIMIZU ,  Takahiro MORI ,  Junjiro SAKAI ,  Satoshi IIDA

IPC: H01L21/4757 ,  H01L21/4763 ,  H01L21/475 ,  H01L23/31 ,  H01L23/532

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

公开(公告)号：US20200259016A1

公开(公告)日：2020-08-13

申请号：US16782823

申请日：2020-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a semiconductor substrate including a first epitaxial layer having a first surface and a second surface, a second epitaxial layer, a buried region formed across the first epitaxial layer and the second epitaxial layer, and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The first region is formed below at least the drain region. The second region has first and second ends in a channel length direction. The first end is located between the body region and the drain region in the channel length direction. The second region extends from the first end toward the second end such that the second end extends below at least the source region. An impurity concentration of the second region is greater than an impurity concentration of the first region.

公开(公告)号：US20170365553A1

公开(公告)日：2017-12-21

申请号：US15696395

申请日：2017-09-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeo TOKUMITSU ,  Takahiro MORI ,  Tetsuya NITTA

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：US20230146397A1

公开(公告)日：2023-05-11

申请号：US17932120

申请日：2022-09-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MORI

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0878 ,  H01L29/7816

Abstract: In a LDMOSFET 100, an “STI structure 11” provided in a drain region including a high concentration drain region 10 and a drift region 12 including the high concentration drain region 10 has a slit region 11A extending in a x-direction, and in plan view, the “STI structure 11” is interposed between the slit region 11A and the high concentration drain region 10.

公开(公告)号：US20190067476A1

公开(公告)日：2019-02-28

申请号：US16059855

申请日：2018-08-09

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/407 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7825 ,  H01L29/7846

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, a first insulation isolation film in which a first trench is formed and a conductive film having a gate electrode, a first buried part buried in the first trench and a first cap part located on the first buried part. The semiconductor substrate has a source region, a drain region, a drift region and a body region. The gate electrode faces the body region which is sandwiched between the drift region and the source region while being insulated from the body region. The first cap part projects longer than the first buried part in a channel width direction which is a direction along a boundary between the body region and the drift region in a planar view on the first insulation isolation film.

公开(公告)号：US20170062608A1

公开(公告)日：2017-03-02

申请号：US15186623

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: To provide an LDMOS semiconductor device having improved properties. A semiconductor device having a source region and a drain region, a channel formation region, a drain insulating region between the channel formation region and the drain region, and a gate electrode is provided. The drain insulating region has a slit exposing therefrom an active region and this slit is placed on the side of the channel formation region with respect to the center of the drain insulating region. This active region is formed as an n type semiconductor region. Such a configuration enables relaxation of an electric field of the drain insulating region on the side of the channel formation region (on the side of the source region). The generation number of hot carriers (hot electrons, hot holes) can therefore be reduced. As a result, a semiconductor device having improved HCI-related properties can be obtained.

Abstract translation: 提供具有改进性能的LDMOS半导体器件。 提供了具有源极区域和漏极区域的沟道形成区域，沟道形成区域和漏极区域之间的漏极绝缘区域以及栅极电极的半导体器件。 漏极绝缘区域具有从其暴露的有源区域的狭缝，并且该狭缝相对于漏极绝缘区域的中心设置在沟道形成区域侧。 该有源区形成为n型半导体区。 这样的结构能够使沟道形成区域（源区域侧）的漏极绝缘区域的电场变得松弛。 因此，能够减少热载流子（热电子，热孔）的产生次数。 结果，可以获得具有改善的与HCl相关的性质的半导体器件。

公开(公告)号：US20150325693A1

公开(公告)日：2015-11-12

申请号：US14705511

申请日：2015-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40

CPC classification number: H01L29/7835 ,  H01L21/28052 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7816

Abstract: A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.

Abstract translation: 场氧化膜从栅电极的下部延伸到漏极区。 多个突起部从栅电极的侧面从源极侧向漏极侧突出。 投影部分在平面图中沿着第二方向（与源区域和漏区域沿着第一方向垂直的方向）并排布置。 在场氧化膜中形成多个开口。 当从第一方向观察时，每个开口位于彼此相邻的突出部分之间。 漏极区侧的开口的边缘比漏极区域更靠近源极区域。 源区域侧的开口的边缘比栅电极的侧面更靠近漏区。

公开(公告)号：US20180342577A1

公开(公告)日：2018-11-29

申请号：US15971130

申请日：2018-05-04

Applicant: Renesas Electronics Corporation

Inventor： Hiroki FUJII ,  Takahiro MORI

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

Abstract: A first comb portion of an n-type well region and a second comb portion of a p− drift region mesh with each other in plan view. A pn junction of the n-type well region and the p− drift region thus has a zigzag shape in plan view. The pn junction formed of the n-type well region and the p− drift region extends from a main surface toward a bottom surface of the isolation trench along a source-side wall surface of an isolation trench.

公开(公告)号：US20180102431A1

公开(公告)日：2018-04-12

申请号：US15837520

申请日：2017-12-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MORI ,  Hiroki FUJII

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/311 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

公开(公告)号：US20170330968A1

公开(公告)日：2017-11-16

申请号：US15665088

申请日：2017-07-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MORI

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7835 ,  H01L21/28052 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7816

Abstract: A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.