公开(公告)号：US09613922B2

公开(公告)日：2017-04-04

申请号：US14582733

申请日：2014-12-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kado ,  Takahiro Naito ,  Toshihiko Sato ,  Hikaru Ikegami ,  Takafumi Kikuchi

IPC: H01L23/04 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L23/28

CPC classification number: H01L24/14 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

公开(公告)号：US09129828B2

公开(公告)日：2015-09-08

申请号：US14027187

申请日：2013-09-14

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Takafumi Kikuchi

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

Abstract translation: 提供了半导体器件，其中具有不同平面尺寸的多个半导体芯片以每个半导体芯片的设计自由度被堆叠。 逻辑芯片，再分配芯片和具有比逻辑芯片更大的平面尺寸的存储器芯片安装在布线板上。 逻辑芯片和存储芯片通过再分配芯片电连接。 再分配芯片包括形成在面向布线板的正面的多个正面电极和形成在与该表面相对的背面的多个背面电极。 再分布芯片具有多个穿通硅通孔，以及形成在前表面或后表面上的多个引线布线，并且电连接多个通孔硅通孔和前表面电极或背表面电极。

公开(公告)号：US20140117541A1

公开(公告)日：2014-05-01

申请号：US14149719

申请日：2014-01-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kado ,  Takahiro Naito ,  Toshihiko Sato ,  Hikaru Ikegami ,  Takafumi Kikuchi

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract translation: 在多芯片模块（MCM）中安装在封装基板（1）的主表面上的三个芯片（2A），（2B）和（2C）中，形成有DRAM的芯片（2A）和芯片 （2B），其上形成有闪速存储器，通过Au凸块（4）与封装基板（1）的布线（5）电连接，并且在芯片（2A）的主表面（下表面）之间形成间隙， （2B）和封装基板（1）的主表面填充有未填充树脂（6）。 其上形成有高速微处理器的芯片（2C）安装在两个芯片（2A）和（2B）上，并且通过Au导线（8）电连接到封装衬底（1）的焊盘（9）。

公开(公告)号：US20150340342A1

公开(公告)日：2015-11-26

申请号：US14818145

申请日：2015-08-04

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Takafumi Kikuchi

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

Abstract translation: 提供了半导体器件，其中具有不同平面尺寸的多个半导体芯片以每个半导体芯片的设计自由度被堆叠。 逻辑芯片，再分配芯片和具有比逻辑芯片更大的平面尺寸的存储器芯片安装在布线板上。 逻辑芯片和存储芯片通过再分配芯片电连接。 再分配芯片包括形成在面向布线板的正面的多个正面电极和形成在与该表面相对的背面的多个背面电极。 再分布芯片具有多个穿通硅通孔，以及形成在前表面或后表面上的多个引线配线，并且电连接多个通孔硅通孔和前表面电极或背表面电极。

公开(公告)号：US20150108639A1

公开(公告)日：2015-04-23

申请号：US14582733

申请日：2014-12-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki Kado ,  Takahiro Naito ,  Toshihiko Sato ,  Hikaru Ikegami ,  Takafumi Kikuchi

IPC: H01L23/00 ,  H01L23/28

CPC classification number: H01L24/14 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract translation: 在多芯片模块（MCM）中安装在封装基板（1）的主表面上的三个芯片（2A），（2B）和（2C）中，形成有DRAM的芯片（2A）和芯片 （2B），其上形成有闪速存储器，通过Au凸块（4）与封装基板（1）的布线（5）电连接，并且在芯片（2A）的主表面（下表面）之间形成间隙， （2B）和封装基板（1）的主表面填充有未填充树脂（6）。 其上形成有高速微处理器的芯片（2C）安装在两个芯片（2A）和（2B）上，并且通过Au导线（8）电连接到封装衬底（1）的焊盘（9）。

公开(公告)号：US08952527B2

公开(公告)日：2015-02-10

申请号：US14149719

申请日：2014-01-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kado ,  Takahiro Naito ,  Toshihiko Sato ,  Hikaru Ikegami ,  Takafumi Kikuchi

IPC: H01L23/04 ,  H01L25/18 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract translation: 在多芯片模块（MCM）中安装在封装基板（1）的主表面上的三个芯片（2A），（2B）和（2C）中，形成有DRAM的芯片（2A）和芯片 （2B），其上形成有闪速存储器，通过Au凸块（4）与封装基板（1）的布线（5）电连接，并且在芯片（2A）的主表面（下表面）之间形成间隙， （2B）和封装基板（1）的主表面填充有未填充树脂（6）。 其上形成有高速微处理器的芯片（2C）安装在两个芯片（2A）和（2B）上，并且通过Au导线（8）电连接到封装衬底（1）的焊盘（9）。

公开(公告)号：US20140077391A1

公开(公告)日：2014-03-20

申请号：US14027187

申请日：2013-09-14

Applicant: Renesas Electronics Corporation

Inventor： Takashi Kikuchi ,  Takafumi Kikuchi

IPC: H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board. The logic chip and the memory chip are electrically connected via the redistribution chip. The redistribution chip includes a plurality of front surface electrodes formed to a front surface facing the wiring board, and a plurality of back surface electrodes formed to a back surface opposite to the surface. The redistribution chip has a plurality of through silicon vias, and a plurality of lead wirings formed to the front surface or the back surface and electrically connecting the plurality of through silicon vias and the front surface electrodes or the back surface electrodes.

Abstract translation: 提供了半导体器件，其中具有不同平面尺寸的多个半导体芯片以每个半导体芯片的设计自由度被堆叠。 逻辑芯片，再分配芯片和具有比逻辑芯片更大的平面尺寸的存储器芯片安装在布线板上。 逻辑芯片和存储芯片通过再分配芯片电连接。 再分配芯片包括形成在面向布线板的正面的多个正面电极和形成在与该表面相对的背面的多个背面电极。 再分布芯片具有多个穿通硅通孔，以及形成在前表面或后表面上的多个引线布线，并且电连接多个通孔硅通孔和前表面电极或背表面电极。

公开(公告)号：US08653655B2

公开(公告)日：2014-02-18

申请号：US13960596

申请日：2013-08-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kado ,  Takahiro Naito ,  Toshihiko Sato ,  Hikaru Ikegami ,  Takafumi Kikuchi

IPC: H01L23/04

CPC classification number: H01L24/14 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract translation: 在多芯片模块（MCM）中安装在封装基板（1）的主表面上的三个芯片（2A），（2B）和（2C）中，形成有DRAM的芯片（2A）和芯片 （2B），其上形成有闪速存储器，通过Au凸块（4）与封装基板（1）的布线（5）电连接，并且在芯片（2A）的主表面（下表面）之间形成间隙， （2B）和封装基板（1）的主表面填充有未填充树脂（6）。 其上形成有高速微处理器的芯片（2C）安装在两个芯片（2A）和（2B）上，并且通过Au导线（8）电连接到封装衬底（1）的焊盘（9）。

公开(公告)号：US20130320571A1

公开(公告)日：2013-12-05

申请号：US13960596

申请日：2013-08-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki Kado ,  Takahiro Naito ,  Toshihiko Sato ,  Hikaru Ikegami ,  Takafumi Kikuchi

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).