公开(公告)号：US20140092688A1

公开(公告)日：2014-04-03

申请号：US14100302

申请日：2013-12-09

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Ishimaru ,  Yasuhiro Shimamoto ,  Hideo Kasai ,  Yutaka Okuyama ,  Tsuyoshi Arigane

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/14 ,  G11C16/30 ,  H01L27/11563 ,  H01L29/42344

Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.

Abstract translation: 在通过热载流子注入进行重写的分闸门MONOS存储器中，保持特性得到改善。 存储单元的选择栅电极连接到选择栅极线，并且存储栅电极连接到存储栅极线。 漏极区域连接到位线，并且源极区域连接到源极线。 此外，阱线连接到其中形成存储单元的p型阱区域。 当要对存储单元进行写入时，通过源极侧注入方法进行写入，同时通过阱线向p型阱区域施加负电压。

公开(公告)号：US09117849B2

公开(公告)日：2015-08-25

申请号：US14325472

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

Abstract translation: 一种形成非易失性半导体器件的方法和装置，包括在第一半导体区域的主表面上形成第一栅极绝缘膜，在第一栅极绝缘膜上形成第一栅电极，形成第二栅极绝缘膜，形成第二栅极 电极，在第一栅电极的第一侧表面上，选择性地去除第二栅极绝缘膜，蚀刻保持在第二栅极电极和第一半导体区域的主表面之间的第二栅极绝缘膜，以形成蚀刻电荷存储层 为了形成第二半导体区域，以自对准的方式将第一半导体区域中的第一杂质引入第二栅电极，使半导体衬底退火，将第二半导体区域延伸到第二栅电极下方的区域。

公开(公告)号：US20140322874A1

公开(公告)日：2014-10-30

申请号：US14325472

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi Akita ,  Daisuke Okada ,  Keisuke Kuwahara ,  Yasufumi Morimoto ,  Yasuhiro Shimamoto ,  Kan Yasui ,  Tsuyoshi Arigane ,  Tetsuya Ishimaru

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/792

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract translation: 插入在存储栅电极和半导体衬底之间的电荷存储层形成为比存储栅电极的栅极长度或绝缘膜的长度短，以使电荷存储层和源极区域的重叠量成为 小于40nm。 因此，在写入状态下，由于在电荷存储层中局部存在的电子和空穴的横向的移动减少，因此可以降低保持高温时的阈值电压的变化。 此外，有效沟道长度为30nm以下，以减少空穴的表观量，使得电子与电荷存储层中的空穴的耦合减小; 因此，可以降低在室温下保持时的阈值电压的变化。

公开(公告)号：US08679915B2

公开(公告)日：2014-03-25

申请号：US13671482

申请日：2012-11-07

Applicant: Renesas Electronics Corporation

Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-ichiro Kimura

IPC: H01L21/00

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract translation: 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。