公开(公告)号：US06222246B1

公开(公告)日：2001-04-24

申请号：US09227594

申请日：1999-01-08

申请人： Tak M. Mak ,  Paul Winer ,  Valluri R. Rao ,  Richard H. Livengood

发明人： Tak M. Mak ,  Paul Winer ,  Valluri R. Rao ,  Richard H. Livengood

IPC分类号： H05K702

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L25/16 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K2201/1053 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/05599

摘要： A flip-chip having a decoupling capacitor electrically coupled to the backside thereof. The flip-chip includes a semiconductor substrate having first and second opposing surfaces with circuit elements formed within the first surface. A plurality of raised bump contacts are located on the first surface and connected to the circuit elements. A plurality of electrical interconnects are also located on or within the second surface and connected to the circuit elements. The electrodes of a decoupling capacitor are electrically coupled to the plurality of electrical interconnects.

摘要翻译： 具有电耦合到其背面的去耦电容器的倒装芯片。 倒装芯片包括具有形成在第一表面内的电路元件的第一和第二相对表面的半导体衬底。 多个突出的凸起触头位于第一表面上并连接到电路元件。 多个电互连也位于第二表面上或第二表面内并连接到电路元件。 去耦电容器的电极电耦合到多个电互连。

公开(公告)号：US6122174A

公开(公告)日：2000-09-19

申请号：US324634

申请日：1999-06-02

申请人： Richard H. Livengood ,  Paul Winer ,  Valluri R. Rao

发明人： Richard H. Livengood ,  Paul Winer ,  Valluri R. Rao

IPC分类号： H01L23/544 ,  H05K1/14

CPC分类号： B24B37/013 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

摘要： An apparatus is disclosed. In one embodiment, the apparatus includes a semiconductor substrate and a second substrate. The semiconductor substrate has a top side and a bottom side. The semiconductor substrate has an integrated circuit and at least one alignment fiducial formed on the top side. The alignment fudicial is aligned with the integrated circuit and the alignment fiducial is accessible from the bottom side. The semiconductor substrate further includes a first set of bond pads on the integrated circuit, the bond pads on the top side. The second substrate has a second set of bond pads corresponding to the first set of bond pads. The semiconductor substrate is coupled to the second substrate at a plurality of solder interconnections disposed between the first and the second set of bond pads.

摘要翻译： 公开了一种装置。 在一个实施例中，该装置包括半导体衬底和第二衬底。 半导体衬底具有顶侧和底侧。 半导体衬底具有集成电路和形成在顶侧上的至少一个对准基准。 对齐方式与集成电路对齐，对准基准可从底部进入。 半导体衬底还包括集成电路上的第一组接合焊盘，顶侧上的接合焊盘。 第二衬底具有对应于第一组接合焊盘的第二组接合焊盘。 半导体衬底在布置在第一组和第二组接合焊盘之间的多个焊料互连处耦合到第二衬底。

公开(公告)号：US5952247A

公开(公告)日：1999-09-14

申请号：US724223

申请日：1996-10-02

申请人： Richard H. Livengood ,  Paul Winer ,  Valluri R. Rao

发明人： Richard H. Livengood ,  Paul Winer ,  Valluri R. Rao

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： B24B37/013 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

摘要： A method for accessing a portion of an integrated circuit formed on top of a semiconductor substrate from the bottom of the semiconductor substrate. First, alignment marks are located which are approximately aligned to the integrated circuit. These alignment marks are then used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access. Finally, an opening is etched into the bottom of the semiconductor substrate at this point.

摘要翻译： 一种用于从半导体衬底的底部访问形成在半导体衬底上的集成电路的一部分的方法。 首先，定位与集成电路近似对准的对准标记。 然后将这些对准标记与集成电路的电路图一起使用，以确定位于集成电路的部分下方的半导体衬底的底点上的点，从业者希望访问。 最后，此刻在半导体衬底的底部刻蚀开口。

公开(公告)号：US5805421A

公开(公告)日：1998-09-08

申请号：US828279

申请日：1997-03-21

申请人： Richard H. Livengood ,  Paul Winer ,  Valluri R. Rao

发明人： Richard H. Livengood ,  Paul Winer ,  Valluri R. Rao

IPC分类号： H01L23/544 ,  H05K1/14

CPC分类号： B24B37/013 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

摘要： An integrated circuit device having alignment marks that are located on the integrated circuit device semiconductor substrate and aligned to the integrated circuit. The alignment marks are used in conjunction with a circuit diagram of the integrated circuit to determine the point on the bottom of the semiconductor substrate residing beneath the portion of the integrated circuit which the practitioner desires to access.

摘要翻译： 一种集成电路器件，具有位于集成电路器件半导体衬底上并与集成电路对准的对准标记。 对准标记与集成电路的电路图一起使用，以确定位于集成电路的部分下面的半导体衬底的底部上的点，从业者希望访问。

公开(公告)号：US06495454B2

公开(公告)日：2002-12-17

申请号：US09953695

申请日：2001-09-12

申请人： Richard H. Livengood ,  Paul Winer ,  Valuri R. M. Rao

发明人： Richard H. Livengood ,  Paul Winer ,  Valuri R. M. Rao

IPC分类号： H01L2144

CPC分类号： H01L21/823871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599

摘要： A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

公开(公告)号：US06355494B1

公开(公告)日：2002-03-12

申请号：US09702052

申请日：2000-10-30

申请人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

发明人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

IPC分类号： H01L2166

CPC分类号： H01L21/67253 ,  H01L22/12 ,  H01L22/26

摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

公开(公告)号：US07232526B2

公开(公告)日：2007-06-19

申请号：US10868245

申请日：2004-06-15

申请人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

发明人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

IPC分类号： B44C1/22

CPC分类号： H01L21/67253 ,  H01L22/12 ,  H01L22/26

摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

摘要翻译： 公开了一种在集成电路制造工艺中控制从半导体衬底去除材料的方法和装置。 该方法和装置利用光源或带电粒子束（电子或离子束）在半导体衬底中形成的至少一个P-N结中感应电流。 在去除材料期间监测感应电流，并且响应于感应电流进行预定的转变而停止或终止该过程。

公开(公告)号：US06780658B2

公开(公告)日：2004-08-24

申请号：US10455143

申请日：2003-06-05

申请人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

发明人： Richard H. Livengood ,  Paul Winer ,  Gary Woods ,  Michael DiBattista

IPC分类号： H01L2166

CPC分类号： H01L21/67253 ,  H01L22/12 ,  H01L22/26

摘要： A method and apparatus for controlling the removal of material from a semiconductor substrate in an integrated circuit fabrication process is disclosed. The method and apparatus utilize a light source or charged particle beam (electron or ion beam) to induce a current in at least one P-N junction formed in the semiconductor substrate. The induced current is monitored during the removal of material and the process is stopped or endpointed in response to the induced current making a predetermined transition.

摘要翻译： 公开了一种在集成电路制造工艺中控制从半导体衬底去除材料的方法和装置。 该方法和装置利用光源或带电粒子束（电子或离子束）在半导体衬底中形成的至少一个P-N结中感应电流。 在去除材料期间监测感应电流，并且响应于感应电流进行预定的转变而停止或终止该过程。

公开(公告)号：US06355950B1

公开(公告)日：2002-03-12

申请号：US09159318

申请日：1998-09-23

申请人： Richard H. Livengood ,  Paul Winer ,  Valuri R. M. Rao

发明人： Richard H. Livengood ,  Paul Winer ,  Valuri R. M. Rao

IPC分类号： H01L2980

CPC分类号： H01L21/823871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5286 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599

摘要： A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

公开(公告)号：US5976980A

公开(公告)日：1999-11-02

申请号：US941887

申请日：1997-09-30

申请人： Richard H. Livengood ,  Paul Winer ,  Valluri R. M. Rao

发明人： Richard H. Livengood ,  Paul Winer ,  Valluri R. M. Rao

IPC分类号： H01J37/305 ,  H01L21/66 ,  H01L23/544 ,  H01L21/00

CPC分类号： H01J37/3056 ,  B24B37/013 ,  H01L22/26 ,  H01L23/544 ,  H01J2237/30466 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025

摘要： A method and an apparatus providing a mechanical probe structure through the back side of an integrated circuit die. In one embodiment, semiconductor substrate is thinned from the back side of the integrated circuit die above a probe target. The probe target is then exposed and a thin insulating layer is formed over the exposed probe target and the nearby semiconductor substrate. The thin insulating layer provides electrical isolation between the exposed probe target and the bulk semiconductor substrate. The thin insulating layer also provides a base insulating platform for a probe pad that is subsequently deposited. After the insulating layer is formed over the exposed probe target and the nearby semiconductor substrate, the probe target is re-exposed through insulating layer such that a probe pad may be deposited over the probe target to provide electrical contact to the original probe target as well as provide a probe pad for mechanical probing purposes from the back side of the integrated circuit die.

摘要翻译： 一种通过集成电路管芯的背面提供机械探针结构的方法和装置。 在一个实施例中，半导体衬底从集成电路管芯的背面被稀释到探针靶上方。 然后暴露探针靶，并且在暴露的探针靶和附近的半导体衬底上形成薄的绝缘层。 薄绝缘层提供暴露的探针靶和体半导体衬底之间的电隔离。 薄绝缘层还提供了随后沉积的探针垫的基底绝缘平台。 在暴露的探针靶和附近的半导体衬底上形成绝缘层之后，通过绝缘层再次暴露探测靶，使得探针焊盘可以沉积在探针上，以提供与原始探测靶的电接触 从集成电路管芯的背面提供用于机械探测目的的探针焊盘。