System and method for clock detection with glitch rejection
    1.
    发明授权
    System and method for clock detection with glitch rejection 有权
    用于具有毛刺抑制的时钟检测的系统和方法

    公开(公告)号:US07352214B2

    公开(公告)日:2008-04-01

    申请号:US11058212

    申请日:2005-02-16

    IPC分类号: G01R19/00

    CPC分类号: H03K5/19 H03K5/1252

    摘要: A system and a method are presented for detecting the presence of at least one clock signal of a defined clock frequency applied to at least one input port of an integrated circuit system, wherein the a first number M of clock pulses related to the at least one clock signal within a predefined cycle period is counted and the counted first number M of clock pulses is compared with a reference number. Depending on the result of the comparison the presence of the at least one clock signal is detected or not.

    摘要翻译: 提出了一种用于检测施加到集成电路系统的至少一个输入端口的定义的时钟频率的至少一个时钟信号的存在的系统和方法,其中与所述至少一个 对预定周期内的时钟信号进行计数,并将计时的第一个数量M的时钟脉冲与参考号进行比较。 根据比较的结果,检测或不检测至少一个时钟信号的存在。

    Method for producing an unbacked tension floor
    2.
    发明授权
    Method for producing an unbacked tension floor 失效
    无背张力地板的制造方法

    公开(公告)号:US4159219A

    公开(公告)日:1979-06-26

    申请号:US859741

    申请日:1977-12-12

    申请人: Richard J. Evans

    发明人: Richard J. Evans

    摘要: An unbacked decorative thermoplastic vinyl resin containing surface covering having a self-induced tension is manufactured by (1) fusing a vinyl resin composition decorative layer and a vinyl resin composition backing layer to a strippable dimensionally stable backing to form a fused thermoplastic decorative surface covering, and (2) removing the strippable backing and rolling the surface covering, thus placing the surface covering under tension and thereby elongating the outward facing layer and compressing the other layer. The composition and structure of the outward facing layer is such that, on unrolling the surface covering, the elongated layer overcomes the compressed layer and the surface covering is stretched to a dimension greater than its original unrolled dimension. On securing the surface covering at its periphery only, the tendency of the surface covering to return to its original dimension, i.e. its elastic memory, creates a self-induced tension therein.

    摘要翻译: 通过(1)将乙烯基树脂组合物装饰层和乙烯基树脂组合物背衬层熔合到可剥离的尺寸稳定的背衬上以形成熔融的热塑性装饰表面覆盖物,制造包含具有自引导张力的表面覆盖物的未背面装饰热塑性乙烯基树脂, (2)去除可剥离背衬并滚动表面覆盖物,由此使表面覆盖物处于张力下,从而拉伸向外的层并压缩另一层。 面向外的层的组成和结构使得在展开表面覆盖物时,细长层克服压缩层,并且将表面覆盖物拉伸至大于其原始展开尺寸的尺寸。 在仅在其外围固定表面覆盖物时,表面覆盖物恢复其原始尺寸(即其弹性记忆体)的趋势在其中产生自身引起的张力。

    Die thinning apparatus
    3.
    发明授权
    Die thinning apparatus 失效
    模具变薄装置

    公开(公告)号:US6010392A

    公开(公告)日:2000-01-04

    申请号:US24912

    申请日:1998-02-17

    IPC分类号: B24B37/30 B24B41/06

    CPC分类号: B24B37/30

    摘要: A fixture for holding a semiconductor die against an abrasive media for the purpose of thinning the die is described. The fixture provides means for aligning the back of the die to a reference plane that is coplanar with the plane of the abrasive and is in contact with the abrasive media during the thinning process.

    摘要翻译: 描述了用于将半导体管芯保持在研磨介质上以用于使管芯变薄的夹具。 夹具提供了将模具的背面与研磨平面共面的参考平面对准的装置,并且在稀化过程中与磨料介质接触。

    Adder increment circuit
    4.
    发明授权

    公开(公告)号:US07139789B2

    公开(公告)日:2006-11-21

    申请号:US10252045

    申请日:2002-09-23

    申请人: Richard J. Evans

    发明人: Richard J. Evans

    IPC分类号: G06F7/50

    摘要: In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating whether a CarryOut signal resulted from the incrementing operation, or whether the CarryOut signal resulted from the addition. The preferred embodiments utilize prefix-type adder circuits using a single carry chain. Alternate embodiments generate a CarryOut signal as a function of the incrementing operation, using either generate and propagate signals or from generate and kill signals from the carry chain.

    Paper carrier stripping method and apparatus
    5.
    发明授权
    Paper carrier stripping method and apparatus 失效
    纸载体剥离方法和装置

    公开(公告)号:US4135675A

    公开(公告)日:1979-01-23

    申请号:US802308

    申请日:1977-06-01

    CPC分类号: B65H39/16 B65H41/00

    摘要: A flooring product is made on a paper carrier and the paper carrier is removed from the flooring just prior to the time the flooring is rolled up. The paper carrier, which is free from the flooring, is wrapped up with the roll of flooring to prevent adhesion between the flooring surfaces in the roll and to provide some physical stability to the roll of flooring when it is standing on its end.

    摘要翻译: 在纸架上制作地板产品,在地板卷起之前,纸架从地板上取下。 没有地板的纸托架用地板卷包裹,以防止卷筒中的地板表面之间的粘合,并且当其在其端部上时向地板卷提供一些物理稳定性。

    Self-induced tension floor
    6.
    发明授权
    Self-induced tension floor 失效
    自我引力的地板

    公开(公告)号:US3990929A

    公开(公告)日:1976-11-09

    申请号:US625082

    申请日:1975-10-23

    申请人: Richard J. Evans

    发明人: Richard J. Evans

    IPC分类号: D06N3/06 E04F15/16 B32B31/00

    摘要: A method of surfacing an area with a surface covering having a decorative wear layer formed of a thermoplastic vinyl resin-containing composition that has been formed by fusing under heat and/or pressure and bonded to a strippable backing before stresses, set up therein during formation, are relieved. The backing is removed prior to installation and the wear layer secured at its perimeter only against movement with respect to the surface being covered and before stresses therein are relieved.

    摘要翻译: 一种具有表面覆盖物的表面覆盖层的方法,所述表面覆盖层具有由含热塑性乙烯基树脂的组合物形成的装饰性耐磨层,所述组合物通过在加热和/或压力下融合而形成,并且在形成之前在应力之间结合到可剥离背衬上 ,放心了。 背衬在安装之前被去除,并且耐磨层在其周边处固定,仅抵抗相对于被覆盖的表面的运动,并且在其中的应力被释放之前。

    Method and apparatus for preventing thermal failure in a semiconductor device through redundancy
    7.
    发明授权
    Method and apparatus for preventing thermal failure in a semiconductor device through redundancy 失效
    通过冗余来防止半导体器件的热故障的方法和装置

    公开(公告)号:US06425092B1

    公开(公告)日:2002-07-23

    申请号:US09098571

    申请日:1998-06-17

    IPC分类号: G06F1100

    CPC分类号: G06F1/206

    摘要: Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.

    摘要翻译: 备用的冗余芯片部分代替基于某些传感器信号处于过热风险的芯片部分。 当这些信号被接收到处于危险中的芯片部分的操作被传送到冗余芯片部分并且处于危险中的芯片部分被关闭时。 在原始芯片部分冷却​​后,它可以作为替代芯片部分自身使用。 传感器信号可以基于温度值,经过的操作时间以及芯片部分内的操作数量或速率。

    Cache memory self test
    10.
    发明授权
    Cache memory self test 失效
    缓存内存自检

    公开(公告)号:US06966017B2

    公开(公告)日:2005-11-15

    申请号:US10173048

    申请日:2002-06-18

    申请人: Richard J. Evans

    发明人: Richard J. Evans

    IPC分类号: G11C29/12 G11C29/00

    CPC分类号: G11C29/12

    摘要: The benefits of on-chip self testing are widely recognized and include the capability to test at high operating speed and independently of external test equipment timing and accuracy limitations. However caches present difficulties since for testing purposes they are conventionally regarded as separate RAM and CAM arrays. The disclosed test engine tests the cache as a whole (i.e., RAM, CAM and comparators together). In the test mode, cache writes are absolutely addressable, selecting a particular entry in a particular way-set during each operation using line addressing and common tag data. This enables read operations to access a specific cache line as if absolutely addressable based on only a partial address and the known tag setting.

    摘要翻译: 片上自检的优点得到广泛认可,包括在高运行速度下测试的能力,并且独立于外部测试设备的时序和精度限制。 然而,缓存存在困难,因为为了测试目的,它们通常被认为是单独的RAM和CAM阵列。 所公开的测试引擎测试整个高速缓存(即RAM,CAM和比较器在一起)。 在测试模式下,缓存写入是绝对可寻址的,使用行寻址和公共标签数据在每个操作期间以特定的方式设置特定条目。 这使得读取操作能够访问特定的高速缓存行,就像基于仅部分地址和已知标签设置完全可寻址的一样。