公开(公告)号：US07622389B1

公开(公告)日：2009-11-24

申请号：US11411353

申请日：2006-04-25

申请人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

发明人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

IPC分类号： H01L21/302

CPC分类号： H01L27/11526 ,  H01L27/11548

摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

摘要翻译： 包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。 然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。 然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。 然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。

公开(公告)号：US08445372B2

公开(公告)日：2013-05-21

申请号：US12644457

申请日：2009-12-22

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/285 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US20090111265A1

公开(公告)日：2009-04-30

申请号：US11924823

申请日：2007-10-26

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/4763

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US20100099249A1

公开(公告)日：2010-04-22

申请号：US12644457

申请日：2009-12-22

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/285 ,  H01L21/3205

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US07691751B2

公开(公告)日：2010-04-06

申请号：US11924823

申请日：2007-10-26

申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC分类号： H01L21/4763

CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US07696038B1

公开(公告)日：2010-04-13

申请号：US11412365

申请日：2006-04-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita ,  Timothy Thurgate ,  Wei Zheng ,  Ashot Melik-Martirosian ,  Angela Hui ,  Chih-Yuh Yang

IPC分类号： H01L21/8238

CPC分类号： H01L27/11568 ,  G11C16/3418 ,  G11C16/3427

摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

摘要翻译： 提供了制造闪速存储器件的方法。 根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。 在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。 第一杂质掺杂区域形成在沟槽下面的衬底内。

公开(公告)号：US07785965B2

公开(公告)日：2010-08-31

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US20080064165A1

公开(公告)日：2008-03-13

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US07915123B1

公开(公告)日：2011-03-29

申请号：US11408866

申请日：2006-04-20

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。

公开(公告)号：US08183623B2

公开(公告)日：2012-05-22

申请号：US13075047

申请日：2011-03-29

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Amol Joshi ,  Kyunghoon Min ,  Chi Chang

IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7883 ,  H01L29/792 ,  Y10S438/954

摘要： A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers.

摘要翻译： 提供了一种双节点存储器件及其制造方法。 在一个实施例中，该方法包括在半导体衬底上形成具有绝缘体层，电荷存储层，缓冲层和牺牲层的分层结构。 这些层被图案化以形成两个间隔开的堆叠和在堆叠之间的暴露的衬底部分。 在暴露的基板上形成栅极绝缘体和栅电极，去除牺牲层和缓冲层。 沉积覆盖电荷存储层的另外的绝缘体层，以在栅电极的每一侧上形成绝缘体存储层 - 绝缘体存储器存储区域。 侧壁间隔件形成在覆盖存储区域的栅电极的侧壁上。 在与栅极间隔开的衬底中形成位线，并且形成与栅电极和侧壁间隔物接触的字线。