公开(公告)号：US5426375A

公开(公告)日：1995-06-20

申请号：US023074

申请日：1993-02-26

申请人： Richard S. Roy ,  Bruce J. Barbara

发明人： Richard S. Roy ,  Bruce J. Barbara

IPC分类号： G01R31/26 ,  G01R31/27 ,  H01L23/544 ,  H01L21/00

CPC分类号： H01L22/34 ,  G01R31/2621 ,  G01R31/275 ,  H01L2924/0002 ,  H01L2924/3011

摘要： MOS integrated circuit fabrication processes may be optimized for yield rather than for hot carrier lifetime by compensating for oversize MOS channel lengths with increased V.sub.cc power supply voltage, and by compensating for undersized MOS device channel lengths with decreased V.sub.cc. Where channel lengths are greater than necessary, V.sub.cc is increased to increase switching times, while still operating the integrated circuit in a regime ensuring at least a minimum hot carrier lifetime. A test MOS device is fabricated on the integrated circuit substrate and in a test mode the test device substrate current I.sub.bb is measured. The measured I.sub.bb is then correlated with known I.sub.bb data to ascertain whether the channel length and DC hot carrier lifetime are acceptable, both for the test device and all MOS devices in the integrated circuit. The measured I.sub.bb value may be used with a look-up table to manually adjust the V.sub.cc power supply to the integrated circuit to compensate for channel length variation. The measured I.sub.bb value may be translated into a desired compensating value of V.sub.cc, and the integrated circuit so labelled, electrically or by package marking. Alternatively, the measured I.sub.bb value may control on an-chip circuit coupled to an off-chip voltage regulator to automatically adjust V.sub.cc to a level ensuring at least a minimum hot carrier lifetime for the integrated circuit.

摘要翻译： 通过用增加的Vcc电源电压补偿过大的MOS沟道长度，并通过用降低的Vcc补偿尺寸过小的MOS器件沟道长度，可以优化MOS集成电路制造工艺，而不是为热载流子寿命进行优化。 在通道长度大于必需的情况下，增加Vcc以增加开关时间，同时仍然以确保至少最小热载流子寿命的状态操作集成电路。 在集成电路基板上制造测试MOS器件，并且在测试模式中测量测试器件衬底电流Ibb。 然后将测量的Ibb与已知的Ibb数据相关联，以确定测试设备和集成电路中的所有MOS器件是否可以接受通道长度和直流热载流子寿命。 测量的Ibb值可以与查找表一起使用，以手动调整集成电路的Vcc电源以补偿通道长度变化。 所测量的Ibb值可以被转换为期望的Vcc补偿值，以及如此标记的集成电路或电子封装或通过封装标记。 或者，测量的Ibb值可以控制耦合到片外电压调节器的片上电路，以将Vcc自动调节到确保集成电路的至少最小热载流子寿命的水平。

公开(公告)号：US08324725B2

公开(公告)日：2012-12-04

申请号：US11160477

申请日：2005-06-24

申请人： Igor Y. Khandros ,  Charles A. Miller ,  Bruce J. Barbara ,  Barbara Vasquez

发明人： Igor Y. Khandros ,  Charles A. Miller ,  Bruce J. Barbara ,  Barbara Vasquez

IPC分类号： H01L23/485 ,  H01L21/00 ,  H01L25/16 ,  H01L25/065

CPC分类号： H01L24/48 ,  H01L23/13 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85186 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.

摘要翻译： 半导体管芯彼此堆叠地堆叠，使得沿着每个管芯的两个边缘定位的端子被暴露。 具有端子的模具的两个边缘可以沿相同的方向定向。 电连接可以将一个管芯上的端子连接到另一个管芯上的端子，并且堆叠可以设置在可以电连接管芯的端子的布线基板上。

公开(公告)号：US20100039739A1

公开(公告)日：2010-02-18

申请号：US12606788

申请日：2009-10-27

申请人： Bruce J. Barbara ,  Charles A. Miller

发明人： Bruce J. Barbara ,  Charles A. Miller

IPC分类号： H02H9/00

CPC分类号： G01R1/36 ,  G01R31/2889

摘要： A fault detection and protection circuit can include a comparing circuit (e.g., a comparator or a detector) that can be connected to a power line supplying power to an electronic device being tested. The comparing circuit can be configured to detect a fault in which the power line is shorted to ground. For example, the electronic device being tested may have a fault in which its power terminals are shorted to ground. Upon detection of such a fault, the comparing circuit activates one or more switches that shunt capacitors or other energy storage devices on the power line to ground. The comparing circuit may alternatively or in addition activate one or more switches that disconnect the power supply supplying power to the electronic device under test from probes contacting the electronic device.

摘要翻译： 故障检测和保护电路可以包括比较电路（例如，比较器或检测器），其可以连接到向所测试的电子设备供电的电力线。 比较电路可以被配置为检测电力线短路到地的故障。 例如，被测试的电子设备可能具有其电源端子短路到地的故障。 在检测到这种故障时，比较电路激活将电力线上的电容器或其他能量存储装置分流到地的一个或多个开关。 比较电路可以替代地或者另外激活一个或多个开关，该开关断开供给被测试的电子设备的电源与接触电子设备的探针的电源。

公开(公告)号：US07609080B2

公开(公告)日：2009-10-27

申请号：US11306186

申请日：2005-12-19

申请人： Charles A. Miller ,  Bruce J. Barbara

发明人： Charles A. Miller ,  Bruce J. Barbara

IPC分类号： G01R31/26

CPC分类号： G01R1/36 ,  G01R31/2889

摘要： A fault detection and protection circuit can include a comparing circuit (e.g., a comparator or a detector) that can be connected to a power line supplying power to an electronic device being tested. The comparing circuit can be configured to detect a fault in which the power line is shorted to ground. For example, the electronic device being tested may have a fault in which its power terminals are shorted to ground. Upon detection of such a fault, the comparing circuit activates one or more switches that shunt capacitors or other energy storage devices on the power line to ground. The comparing circuit may alternatively or in addition activate one or more switches that disconnect the power supply supplying power to the electronic device under test from probes contacting the electronic device.

摘要翻译： 故障检测和保护电路可以包括比较电路（例如，比较器或检测器），其可以连接到向所测试的电子设备供电的电力线。 比较电路可以被配置为检测电力线短路到地的故障。 例如，被测试的电子设备可能具有其电源端子短路到地的故障。 在检测到这种故障时，比较电路激活将电力线上的电容器或其他能量存储装置分流到地的一个或多个开关。 比较电路可以替代地或者另外激活一个或多个开关，该开关断开供给被测试的电子设备的电源与接触电子设备的探针的电源。

公开(公告)号：US3965460A

公开(公告)日：1976-06-22

申请号：US537992

申请日：1975-01-02

申请人： Bruce J. Barbara

发明人： Bruce J. Barbara

IPC分类号： G11C11/4094 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C11/4094

摘要： A speed-up circuit, which may be used to speed up the sensing of a bit-sense line of an MOS RAM, includes a crosscoupled latch circuit having an output suitable for coupling to an output circuit for the RAM. A plurality of bit-sense lines of the RAM storage array are coupled to load circuitry for one side of the latch circuit. When partial discharging of a bit-sense line by a selected memory cell occurs, the latch circuit switches state and provides feedback internal to the latch circuit and other feedback external to the latch circuit to aid the selected memory storage cell in discharging a bit-sense line much more rapidly than could have been achieved by the action of the selected storage cell alone, and also assures complete discharging of the bit-sense line, which avoids destroying stored data in the selected memory cell during a refresh cycle. The external feedback is coupled to discharge devices connected to the various bit-sense lines serving various sections of the memory array.

摘要翻译： 可用于加速MOS RAM的位读取行的感测的加速电路包括具有适于耦合到RAM的输出电路的输出的交叉耦合的锁存电路。 RAM存储阵列的多个位读取行被耦合到锁存电路的一侧的负载电路。 当选择的存储单元发生位读取行的局部放电时，锁存电路切换状态并提供锁存电路内部的反馈和锁存电路外的其他反馈，以帮助选定的存储器单元放电一位 线比通过所选择的存储单元的动作可以实现的快得多，并且还确保位读取线的完全放电，这避免了在刷新周期期间破坏所选存储单元中的存储数据。 外部反馈耦合到连接到服务于存储器阵列的各个部分的各种位读取线的放电装置。