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    Gain and phase constrained adaptive equalizing filter in a sampled amplitude read channel for magnetic recording
    1.
    发明授权
    Gain and phase constrained adaptive equalizing filter in a sampled amplitude read channel for magnetic recording 有权
    用于磁记录的采样振幅读通道中的增益和相位约束自适应均衡滤波器

    公开(公告)号：US06208481B1

    公开(公告)日：2001-03-27

    申请号：US09342167

    申请日：1999-06-28

    申请人： Mark S. Spurbeck ,  Li Du ,  Trent O. Dudley ,  William G. Bliss ,  German S. Feyh ,  Richard T. Behrens

    发明人： Mark S. Spurbeck ,  Li Du ,  Trent O. Dudley ,  William G. Bliss ,  German S. Feyh ,  Richard T. Behrens

    IPC分类号： G11B5035

    CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/1403 ,  H04L7/0029 ,  H04L7/0062

    摘要： A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

    摘要翻译： 用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据 公开了使用维特比序列检测器。 为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。 此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

    Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording
    3.
    发明授权
    Adaptive equalization and interpolated timing recovery in a sampled amplitude read channel for magnetic recording 失效
    用于磁记录的采样振幅读通道中的自适应均衡和内插定时恢复

    公开(公告)号：US06819514B1

    公开(公告)日：2004-11-16

    申请号：US08640351

    申请日：1996-04-30

    申请人： Richard T. Behrens ,  Li Du ,  William G. Bliss ,  David E. Reed ,  Mark S. Spurbeck

    发明人： Richard T. Behrens ,  Li Du ,  William G. Bliss ,  David E. Reed ,  Mark S. Spurbeck

    IPC分类号： G11B5035

    CPC分类号： G11B20/10194 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/1258 ,  G11B20/1876

    摘要： A sampled amplitude read channel for magnetic disk recording which asynchronously samples the analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector is disclosed. To minimize interference from the timing and gain control loops, the phase and magnitude response of the adaptive equalizer filter are constrained at a predetermined frequency using an optimal orthogonal projection operation as a modification to a least mean square (LMS) adaptation algorithm. Further, with interpolated timing recovery, the equalizer filter and its associated latency are removed from the timing recovery loop, thereby allowing a higher order discrete time filter and a lower order analog filter.

    摘要翻译： 用于磁盘记录的采样幅度读取通道，其异步采样模拟读取信号，根据目标部分响应对所得离散时间采样值进行自适应均衡，通过内插定时恢复提取同步采样值，并从同步采样值检测数字数据 公开了使用维特比序列检测器。 为了最小化来自定时和增益控制环路的干扰，使用最佳正交投影操作将自适应均衡器滤波器的相位和幅度响应约束在预定频率，作为对最小均方（LMS）适配算法的修改。 此外，通过内插定时恢复，均衡器滤波器及其相关等待时间从定时恢复环路中移除，从而允许较高阶离散时间滤波器和较低阶模拟滤波器。

    Sampled amplitude read channel employing interpolated timing recovery
    4.
    发明授权
    Sampled amplitude read channel employing interpolated timing recovery 失效
    采用内插时序恢复的采样幅度读取通道

    公开(公告)号：US5696639A

    公开(公告)日：1997-12-09

    申请号：US440508

    申请日：1995-05-12

    申请人： Mark S. Spurbeck ,  Richard T. Behrens ,  German S. Feyh

    发明人： Mark S. Spurbeck ,  Richard T. Behrens ,  German S. Feyh

    IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H04L7/02 ,  H04L7/04 ,  C11B5/09

    CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/1403 ,  H04L7/0029 ,  G11B20/1258 ,  H04L2007/047 ,  H04L7/04

    摘要： A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.

    摘要翻译： 一种采样振幅读通道，用于通过从离散时间内插样本值序列中检测数字数据来读取存储在磁介质上的信息，该内插样本值是通过内插由模拟读取中的采样脉冲产生的离散时间通道采样值序列而产生的 来自位于磁介质上的磁读头的信号。 写入VFO产生写入时钟，用于以预定的波特率为所选区域将数字数据写入磁介质，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。 采样设备以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间通道采样序列。 信道样本根据预定的部分响应（PR4，EPR4，EEPR4等）由离散时间均衡滤波器进行均衡。 内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。 定时恢复电路还产生用于对离散时间序列检测器进行计时的数据时钟，用于从内插样本值检测数字数据。

    Cost reduced interpolated timing recovery in a sampled amplitude read channel
    6.
    发明授权
    Cost reduced interpolated timing recovery in a sampled amplitude read channel 失效
    采样幅度读通道中成本降低的插值定时恢复

    公开(公告)号：US5760984A

    公开(公告)日：1998-06-02

    申请号：US546162

    申请日：1995-10-20

    申请人： Mark S. Spurbeck ,  Richard T. Behrens

    发明人： Mark S. Spurbeck ,  Richard T. Behrens

    IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H04L7/02

    CPC分类号： H04L7/0029 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/10064 ,  G11B20/10074 ,  G11B20/1403 ,  G11B20/1258 ,  G11B2020/1234 ,  H04L2007/047

    摘要： A sampled amplitude read channel reads information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate, and the channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector which detects the digital data from the interpolated sample values. In a cost reduced implementation, the interpolation filter coefficients are computed in real time as a function of the interpolation interval .tau..

    摘要翻译： 采样幅度读取通道通过从离散时间内插采样值序列中检测数字数据来读取存储在磁性介质上的信息，内插采样值是通过内插由模拟读取信号中的采样脉冲产生的离散时间通道采样值序列而产生的 从位于磁介质上的磁读头。 写入VFO产生写入时钟，用于以预定的波特率为所选区域将数字数据写入磁介质，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。 采样装置以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间信道采样序列，并且通过离散时间均衡滤波器根据预定的部分响应（ PR4，EPR4，EEPR4等）。 内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。 定时恢复电路还产生数据时钟，用于计时离散时间序列检测器，其从插值的采样值检测数字数据。 在成本降低的实现中，内插滤波器系数作为内插间隔τ的函数被实时计算。

    Sampled amplitude read channel employing interpolated timing recovery
    8.
    发明授权
    Sampled amplitude read channel employing interpolated timing recovery 失效
    采用内插时序恢复的采样幅度读取通道

    公开(公告)号：US5909332A

    公开(公告)日：1999-06-01

    申请号：US834354

    申请日：1997-04-16

    申请人： Mark S. Spurbeck ,  Richard T. Behrens

    发明人： Mark S. Spurbeck ,  Richard T. Behrens

    IPC分类号： G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  H04L7/02 ,  H04L7/04 ,  G11B5/09

    CPC分类号： G11B20/10009 ,  G11B20/10037 ,  G11B20/10055 ,  G11B20/1403 ,  H04L7/0029 ,  G11B20/1258 ,  H04L2007/047 ,  H04L7/04

    摘要： A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. The channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval .tau. and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector for detecting the digital data from the interpolated sample values.

    摘要翻译： 一种采样振幅读通道，用于通过从离散时间内插样本值序列中检测数字数据来读取存储在磁介质上的信息，该内插样本值是通过内插由模拟读取中的采样脉冲产生的离散时间通道采样值序列而产生的 来自位于磁介质上的磁读头的信号。 写入VFO产生写入时钟，用于以预定的波特率为所选区域将数字数据写入磁介质，并且在读回时，写入VFO以略高于写入频率的频率产生采样时钟。 采样设备以采样时钟速率对模拟读取信号进行采样，以产生不与波特率同步的离散时间通道采样序列。 信道样本根据预定的部分响应（PR4，EPR4，EEPR4等）由离散时间均衡滤波器进行均衡。 内插定时恢复电路响应于均衡信道采样，计算内插间隔τ，并且响应于此产生基本上与波特率同步的内插采样值。 定时恢复电路还产生用于对离散时间序列检测器进行计时的数据时钟，用于从内插样本值检测数字数据。

    Digital architecture for radio-frequency apparatus and associated methods
    9.
    发明授权
    Digital architecture for radio-frequency apparatus and associated methods 有权
    射频设备数字架构及相关方法

    公开(公告)号：US07702362B2

    公开(公告)日：2010-04-20

    申请号：US11287995

    申请日：2005-11-28

    申请人： Richard T. Behrens ,  Tod Paulus ,  Mark S. Spurbeck ,  Vishnu S. Srinivasan ,  Donald A. Kerth ,  Jeffrey W. Scott ,  G. Tyson Tuttle ,  G. Diwakar Vishakhadatta

    发明人： Richard T. Behrens ,  Tod Paulus ,  Mark S. Spurbeck ,  Vishnu S. Srinivasan ,  Donald A. Kerth ,  Jeffrey W. Scott ,  G. Tyson Tuttle ,  G. Diwakar Vishakhadatta

    IPC分类号： H04B1/38 ,  H04M1/00

    CPC分类号： H04B1/28 ,  H04B1/0003 ,  H04B1/38 ,  H04B1/406 ,  H04B15/02 ,  H04B15/04 ,  H04B2215/064

    摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

    摘要翻译： 射频（RF）接收机包括接收机模拟电路和接收机数字电路。 接收器模拟电路驻留在第一集成电路内，并且接收器数字电路位于第二集成电路内。 第二集成电路通过一位数字接口耦合到第一集成电路。 接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。 接收机模拟电路将数字信号提供给接收机数字电路。 接收机数字电路包括数字下变频器电路，其将数字信号与中频（IF）本地振荡器（LO）信号混合以产生数字下变频信号。 接收机数字电路还包括数字滤波器电路，其对数字下变频信号进行滤波以产生经滤波的数字信号。

    DIGITAL ARCHITECTURE FOR RADIO-FREQUENCY APPARATUS AND ASSOCIATED METHODS
    10.
    发明申请
    DIGITAL ARCHITECTURE FOR RADIO-FREQUENCY APPARATUS AND ASSOCIATED METHODS 有权
    无线电频率设备数码建筑及相关方法

    公开(公告)号：US20100166124A1

    公开(公告)日：2010-07-01

    申请号：US12715361

    申请日：2010-03-01

    申请人： Richard T. Behrens ,  Tod Paulus ,  Mark S. Spurbeck ,  Vishnu S. Srinivasan ,  Donald A. Kerth ,  Jeffrey W. Scott ,  G. Tyson Tuttle ,  G. Diwakar Vishakhadatta

    发明人： Richard T. Behrens ,  Tod Paulus ,  Mark S. Spurbeck ,  Vishnu S. Srinivasan ,  Donald A. Kerth ,  Jeffrey W. Scott ,  G. Tyson Tuttle ,  G. Diwakar Vishakhadatta

    IPC分类号： H04L27/00 ,  H04B1/10

    CPC分类号： H04B1/28 ,  H04B1/0003 ,  H04B1/38 ,  H04B1/406 ,  H04B15/02 ,  H04B15/04 ,  H04B2215/064

    摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

    摘要翻译： 射频（RF）接收机包括接收机模拟电路和接收机数字电路。 接收器模拟电路驻留在第一集成电路内，并且接收器数字电路位于第二集成电路内。 第二集成电路通过一位数字接口耦合到第一集成电路。 接收机模拟电路接收RF信号并处理所接收的RF信号以产生数字信号。 接收机模拟电路将数字信号提供给接收机数字电路。 接收机数字电路包括数字下变频器电路，其将数字信号与中频（IF）本地振荡器（LO）信号混合以产生数字下变频信号。 接收机数字电路还包括数字滤波器电路，其对数字下变频信号进行滤波以产生经滤波的数字信号。