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公开(公告)号：US07855918B2
公开(公告)日：2010-12-21
申请号：US12144645
申请日：2008-06-24
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴 通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元 。
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公开(公告)号：US07952934B2
公开(公告)日：2011-05-31
申请号：US12943937
申请日：2010-11-11
IPC分类号： G11C11/34
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 用于对存储器结构进行编程的方法包括：分别向第一存储单元和第二存储单元的栅极提供第一栅极偏置电压和第二栅极偏置电压，提升第一存储单元的沟道电压的绝对值以产生 电子和空穴对，通过栅极引起的漏极泄漏或带对带通隧道在第二存储单元的漏极处，并且将所产生的电子和空穴对的空穴注入到第一存储器单元的电荷存储装置中以对 第一个存储单元
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公开(公告)号：US20110051526A1
公开(公告)日：2011-03-03
申请号：US12943937
申请日：2010-11-11
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 用于对存储器结构进行编程的方法包括：分别向第一存储单元和第二存储单元的栅极提供第一栅极偏置电压和第二栅极偏置电压，提升第一存储单元的沟道电压的绝对值以产生 电子和空穴对，通过栅极引起的漏极泄漏或带对带通隧道在第二存储单元的漏极处，并且将所产生的电子和空穴对的空穴注入到第一存储器单元的电荷存储装置中以对 第一个存储单元
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公开(公告)号：US20090168531A1
公开(公告)日：2009-07-02
申请号：US12144645
申请日：2008-06-24
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the first memory cell and the second memory cell, boosting the absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the electron of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell.
摘要翻译： 存储器结构包括位于相同位线并与第一存储器单元相邻的第一存储器单元和第二存储器单元。 每个存储单元包括衬底，源极，漏极，电荷存储器件和栅极。 一种用于对存储器结构进行编程的方法包括分别向第一存储单元和第二存储单元提供第一栅极偏置电压和第二栅极偏置电压，提高第一存储单元的沟道电压的绝对值以产生电子和空穴 通过栅极引起的漏极泄漏或带对带隧穿在第二存储单元的漏极处对，并将所产生的电子和空穴对的电子注入到第一存储单元的电荷存储装置中，以对第一存储单元 。
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公开(公告)号：US20130083598A1
公开(公告)日：2013-04-04
申请号：US13468043
申请日：2012-05-10
申请人： Kai-Yuan Hsiao , Wen-Yuan Lee , Yun-Jen Ting , Cheng-Jye Liu , Wein-Town Sun
发明人： Kai-Yuan Hsiao , Wen-Yuan Lee , Yun-Jen Ting , Cheng-Jye Liu , Wein-Town Sun
IPC分类号： G11C16/06
CPC分类号： G11C16/0466 , G11C14/00 , G11C14/0063 , G11C16/0416 , H01L27/11565 , H01L29/792
摘要： Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.
摘要翻译： 存储器的多个存储单元的每个存储单元具有阱，源极和漏极区，存储层和栅极。 存储单元是矩阵。 相同的列漏极区域连接到相同的位线，相同的行栅极连接到相同的字线，并且相同的列源区域连接到相同的源极线。 通过将第一电压施加到电连接到多个存储器单元的存储单元的字线来对存储器进行编程，将不同于第一电压的第二电压施加至少编程阈值至与存储器电连接的位线 将与所述第一电压不同的第三电压施加至所述编程阈值至与所述存储单元电连接的源极线，以及向所述多个存储单元施加衬底电压。
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6.发明申请公开(公告)号：US20120087192A1
公开(公告)日：2012-04-12
申请号：US13315299
申请日：2011-12-09
申请人： Shang-Wei Fang , Ying-Je Chen , Hong-Yi Liao , Wein-Town Sun , Yu-Hsiung Tsai , Cheng-Jye Liu
发明人： Shang-Wei Fang , Ying-Je Chen , Hong-Yi Liao , Wein-Town Sun , Yu-Hsiung Tsai , Cheng-Jye Liu
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/3468
摘要： A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.
摘要翻译： 一种对包括选择晶体管和存储晶体管的非易失性存储单元进行编程的方法包括：将预设极限电流施加到存储单元的第一输入端，向限流电路施加极限电压，该限流电路电连接到存储器的第二输入端 施加限制电压以稳定存储器单元的电压降，以及将斜坡栅极电压施加到存储器单元，以由由限流电路确定的预置限制电流对存储单元进行编程。
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公开(公告)号：US20090235328A1
公开(公告)日：2009-09-17
申请号：US12258428
申请日：2008-10-26
申请人： Tung-Cheng Kuo , Ching-Sung Yang , Ruei-Ling Lin , Cheng-Jye Liu
发明人： Tung-Cheng Kuo , Ching-Sung Yang , Ruei-Ling Lin , Cheng-Jye Liu
IPC分类号： G06F21/00
CPC分类号： G06F21/79
摘要： A data accessing system includes a host and a storage device. The host has a security setup function and includes a first identity code storage block. The host executes the security setup function to set a first identity code according to a second identity code, and the second identity code is stored into the first identity code storage block. The storage device has a security check function and includes a second identity code storage block to store the second identity code, and the storage device executes the security check function to determine if the host is allowed to access the storage device according to the first identity code.
摘要翻译： 数据访问系统包括主机和存储设备。 主机具有安全设置功能，并且包括第一身份码存储块。 主机执行安全设置功能以根据第二身份码设置第一身份码，并且将第二身份码存储到第一身份码存储块中。 存储装置具有安全检查功能，并且包括存储第二身份码的第二身份码存储块，并且存储装置执行安全检查功能，以确定主机是否被允许根据第一身份码访问存储装置 。
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公开(公告)号：US06608778B1
公开(公告)日：2003-08-19
申请号：US10064800
申请日：2002-08-19
申请人： Cheng-Jye Liu , Tai-Liang Hsiung , Chia-Hsing Chen
发明人： Cheng-Jye Liu , Tai-Liang Hsiung , Chia-Hsing Chen
IPC分类号： G11C1604
CPC分类号： G11C16/107 , G11C16/0475 , G11C16/3477
摘要： The present invention provides a method for operating a NROM device, where the source and drain are surrounded by a heavy doping. When programming the NROM device, a more positive source bias and a more negative substrate bias is used to increase the body effect of the substrate for reducing the current require for Channel Hot Electron Injection (CHEI) programming. Furthermore, before erasing the NROM array, a pre-programming operation is performed to program every single memory cell of the NROM array to the written state for preventing over-erasing of the memory cells.
摘要翻译： 本发明提供了一种用于操作NROM器件的方法，其中源极和漏极被重掺杂包围。 当编程NROM器件时，使用更正的源极偏压和更负的衬底偏压来增加衬底的体效应，以减少通道热电注入（CHEI）编程的电流要求。 此外，在擦除NROM阵列之前，执行预编程操作以将NROM阵列的每个单个存储器单元编程为写入状态，以防止存储器单元的过度擦除。
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公开(公告)号：US06580135B2
公开(公告)日：2003-06-17
申请号：US10104849
申请日：2002-03-22
IPC分类号： H01L2976
CPC分类号： H01L29/792
摘要： A silicon nitride read only memory and associated method of data programming and erasing. The read only memory includes a first type ion-doped semiconductor substrate, an oxide-nitride-oxide (ONO) composite layer over the semiconductor substrate, a first type ion-doped gate conductive layer over the ONO layer and a second type ion doped source/drain region in the substrate on each side of the ONO layer, wherein the second type ions have an electrical polarity opposite to the first type ions. Data is programmed into the silicon nitride read only memory by channel hot electron injection and data is erased from the silicon nitride read only memory by negative gate channel erase method. Since the gate conductive layer and the channel layer are identically doped, the energy gap between the two layers reduced. Hence, operating voltage of the gate terminal is lowered and damage to the tunnel oxide layer by hot holes is reduced.
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10.发明授权公开(公告)号：US08467245B2
公开(公告)日：2013-06-18
申请号：US13315299
申请日：2011-12-09
申请人： Shang-Wei Fang , Ying-Je Chen , Hong-Yi Liao , Wein-Town Sun , Yu-Hsiung Tsai , Cheng-Jye Liu
发明人： Shang-Wei Fang , Ying-Je Chen , Hong-Yi Liao , Wein-Town Sun , Yu-Hsiung Tsai , Cheng-Jye Liu
CPC分类号： G11C16/10 , G11C16/3468
摘要： A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.
摘要翻译： 一种对包括选择晶体管和存储晶体管的非易失性存储单元进行编程的方法包括：将预设极限电流施加到存储单元的第一输入端，向限流电路施加极限电压，该限流电路电连接到存储器的第二输入端 施加限制电压以稳定存储器单元的电压降，以及将斜坡栅极电压施加到存储器单元，以由由限流电路确定的预置限制电流对存储单元进行编程。
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