公开(公告)号：US08467245B2

公开(公告)日：2013-06-18

申请号：US13315299

申请日：2011-12-09

申请人： Shang-Wei Fang ,  Ying-Je Chen ,  Hong-Yi Liao ,  Wein-Town Sun ,  Yu-Hsiung Tsai ,  Cheng-Jye Liu

发明人： Shang-Wei Fang ,  Ying-Je Chen ,  Hong-Yi Liao ,  Wein-Town Sun ,  Yu-Hsiung Tsai ,  Cheng-Jye Liu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/3468

摘要： A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

摘要翻译： 一种对包括选择晶体管和存储晶体管的非易失性存储单元进行编程的方法包括：将预设极限电流施加到存储单元的第一输入端，向限流电路施加极限电压，该限流电路电连接到存储器的第二输入端 施加限制电压以稳定存储器单元的电压降，以及将斜坡栅极电压施加到存储器单元，以由由限流电路确定的预置限制电流对存储单元进行编程。

公开(公告)号：US20120087192A1

公开(公告)日：2012-04-12

申请号：US13315299

申请日：2011-12-09

申请人： Shang-Wei Fang ,  Ying-Je Chen ,  Hong-Yi Liao ,  Wein-Town Sun ,  Yu-Hsiung Tsai ,  Cheng-Jye Liu

发明人： Shang-Wei Fang ,  Ying-Je Chen ,  Hong-Yi Liao ,  Wein-Town Sun ,  Yu-Hsiung Tsai ,  Cheng-Jye Liu

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3468

摘要： A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.

摘要翻译： 一种对包括选择晶体管和存储晶体管的非易失性存储单元进行编程的方法包括：将预设极限电流施加到存储单元的第一输入端，向限流电路施加极限电压，该限流电路电连接到存储器的第二输入端 施加限制电压以稳定存储器单元的电压降，以及将斜坡栅极电压施加到存储器单元，以由由限流电路确定的预置限制电流对存储单元进行编程。

公开(公告)号：US20140016414A1

公开(公告)日：2014-01-16

申请号：US13546036

申请日：2012-07-11

申请人： Yu-Hsiung Tsai ,  Yuan-Tai Lin ,  Ching-Yuan Lin ,  Chao-Wei Kuo ,  Shang-Wei Fang ,  Wein-Town Sun

发明人： Yu-Hsiung Tsai ,  Yuan-Tai Lin ,  Ching-Yuan Lin ,  Chao-Wei Kuo ,  Shang-Wei Fang ,  Wein-Town Sun

IPC分类号： G11C16/04

CPC分类号： G11C13/0069 ,  G11C13/0064 ,  G11C16/04 ,  G11C16/12

摘要： The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

摘要翻译： 本发明提供一种包括存储单元，限流器和编程电压发生器的闪速存储器。 响应于编程电流和编程电压对存储单元进行编程。 电流限制器通过数据线信号（例如数据线电压）反映节目电流的量。 程序电压发生器响应于数据线电压产生并控制编程电压，使得编程电流可以跟踪恒定的参考电流。

公开(公告)号：US08369154B2

公开(公告)日：2013-02-05

申请号：US12944711

申请日：2010-11-11

申请人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

发明人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/3468

摘要： A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

摘要翻译： 用于减少编程电流和提高可靠性的非易失性存储器件包括存储单元阵列，写入电路和验证电路。 存储单元阵列包括布置在存储单元阵列的位线和字线矩阵的交叉点处的存储单元。 写电路为每个字线提供多个可变脉冲进行编程。 多个可变脉冲具有预定的幅度，以在编程操作期间降低导通电流，保持栅极注入电流大致最大。 验证电路在编程操作期间感测导通电流的变化，并且如果在编程操作期间感测到的传导电流达到预定值，则禁止编程操作。

公开(公告)号：US08817543B2

公开(公告)日：2014-08-26

申请号：US13546036

申请日：2012-07-11

申请人： Yu-Hsiung Tsai ,  Yuan-Tai Lin ,  Ching-Yuan Lin ,  Chao-Wei Kuo ,  Shang-Wei Fang ,  Wein-Town Sun

发明人： Yu-Hsiung Tsai ,  Yuan-Tai Lin ,  Ching-Yuan Lin ,  Chao-Wei Kuo ,  Shang-Wei Fang ,  Wein-Town Sun

IPC分类号： G11C11/34 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0064 ,  G11C16/04 ,  G11C16/12

摘要： The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.

摘要翻译： 本发明提供一种包括存储单元，限流器和编程电压发生器的闪速存储器。 响应于编程电流和编程电压对存储单元进行编程。 电流限制器通过数据线信号（例如数据线电压）反映节目电流的量。 程序电压发生器响应于数据线电压产生并控制编程电压，使得编程电流可以跟踪恒定的参考电流。

公开(公告)号：US20110235427A1

公开(公告)日：2011-09-29

申请号：US12944711

申请日：2010-11-11

申请人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

发明人： Ying-Je Chen ,  Yun-Jen Ting ,  Wein-Town Sun ,  Kai-Yuan Hsiao ,  Cheng-Jye Liu

IPC分类号： G11C16/12 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C16/3468

摘要： A nonvolatile memory device for reducing programming current and improving reliability comprises a memory cell array, a write circuit, and a verification circuit. The memory cell array comprises memory cells arranged at crossing points of a bit-line and word-line matrix of the memory cell array. The write circuit provides multiple variable pulses to each word-line for programming. The multiple variable pulses have predetermined amplitude for keeping gate injection current roughly maximum while lowering conduction current during programming operation. The verification circuit senses variation of the conduction current during the programming operation, and disables the programming operation if the sensed conduction current during the programming operation reaches a predetermined value.

摘要翻译： 用于减少编程电流和提高可靠性的非易失性存储器件包括存储单元阵列，写入电路和验证电路。 存储单元阵列包括布置在存储单元阵列的位线和字线矩阵的交叉点处的存储单元。 写电路为每个字线提供多个可变脉冲进行编程。 多个可变脉冲具有预定的幅度，以在编程操作期间降低导通电流，保持栅极注入电流大致最大。 验证电路在编程操作期间感测导通电流的变化，并且如果在编程操作期间感测到的传导电流达到预定值，则禁止编程操作。

公开(公告)号：US20130064027A1

公开(公告)日：2013-03-14

申请号：US13231980

申请日：2011-09-14

申请人： Meng-Yi Wu ,  Wein-Town Sun ,  Yen-Tai Lin ,  Cheng-Jye Liu ,  Chiun-Chi Shen

发明人： Meng-Yi Wu ,  Wein-Town Sun ,  Yen-Tai Lin ,  Cheng-Jye Liu ,  Chiun-Chi Shen

IPC分类号： G11C29/00

CPC分类号： G11C29/021 ,  G11C11/40 ,  G11C29/028 ,  G11C29/50016 ,  G11C2029/5002

摘要： By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.

摘要翻译： 通过根据指示存储单元的未测试电容器的电容的测量电容结果来调节存储器中的存储单元的工作电压，可以总是根据所测量的电容结果确定存储单元的适当工作电压。 测量的电容结果表示指示存储单元的栅极电介质的特性的未测试电容器的电容是否高于或低于参考电容器，并且通过放大表示参考电容器的电容的两个电压之间的差来产生 和被测电容器的电容。

公开(公告)号：US08837219B2

公开(公告)日：2014-09-16

申请号：US13468043

申请日：2012-05-10

申请人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

发明人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

IPC分类号： G11C16/04 ,  G11C14/00 ,  H01L27/115 ,  H01L29/792

CPC分类号： G11C16/0466 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/0416 ,  H01L27/11565 ,  H01L29/792

摘要： Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

摘要翻译： 存储器的多个存储单元的每个存储单元具有阱，源极和漏极区，存储层和栅极。 存储单元是矩阵。 相同的列漏极区域连接到相同的位线，相同的行栅极连接到相同的字线，并且相同的列源区域连接到相同的源极线。 通过将第一电压施加到电连接到多个存储器单元的存储单元的字线来对存储器进行编程，将不同于第一电压的第二电压施加至少编程阈值至与存储器电连接的位线 将与所述第一电压不同的第三电压施加至所述编程阈值至与所述存储单元电连接的源极线，以及向所述多个存储单元施加衬底电压。

公开(公告)号：US20130083598A1

公开(公告)日：2013-04-04

申请号：US13468043

申请日：2012-05-10

申请人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

发明人： Kai-Yuan Hsiao ,  Wen-Yuan Lee ,  Yun-Jen Ting ,  Cheng-Jye Liu ,  Wein-Town Sun

IPC分类号： G11C16/06

CPC分类号： G11C16/0466 ,  G11C14/00 ,  G11C14/0063 ,  G11C16/0416 ,  H01L27/11565 ,  H01L29/792

摘要： Each memory cell of a plurality of memory cells of a memory has a well, source and drain regions, a storage layer, and a gate. The memory cells are in a matrix. Same column drain regions connect to the same bit line, same row gates connect to the same word line, and same column source regions connect to the same source line. The memory is programmed by applying a first voltage to a word line electrically connected to a memory cell of the plurality of memory cells, applying a second voltage different from the first voltage by at least a programming threshold to a bit line electrically connected to the memory cell, applying a third voltage different from the first voltage by at least the programming threshold to a source line electrically connected to the memory cell, and applying a substrate voltage to the plurality of memory cells.

摘要翻译： 存储器的多个存储单元的每个存储单元具有阱，源极和漏极区，存储层和栅极。 存储单元是矩阵。 相同的列漏极区域连接到相同的位线，相同的行栅极连接到相同的字线，并且相同的列源区域连接到相同的源极线。 通过将第一电压施加到电连接到多个存储器单元的存储单元的字线来对存储器进行编程，将不同于第一电压的第二电压施加至少编程阈值至与存储器电连接的位线 将与所述第一电压不同的第三电压施加至所述编程阈值至与所述存储单元电连接的源极线，以及向所述多个存储单元施加衬底电压。

公开(公告)号：US08526240B2

公开(公告)日：2013-09-03

申请号：US13211339

申请日：2011-08-17

申请人： Chun-Yuan Lo ,  Wein-Town Sun

发明人： Chun-Yuan Lo ,  Wein-Town Sun

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3459

摘要： A programming method includes the following steps. A preset programming voltage is applied to a memory cell to program the memory cell. A first verify voltage is applied to the memory cell to detect a programming result of the memory cell. A programming voltage applied on the memory cell is adjusted according to the programming result of the memory cell. A flash memory is also provided.

摘要翻译： 编程方法包括以下步骤。 将预设的编程电压施加到存储器单元以对存储器单元进行编程。 第一验证电压被施加到存储器单元以检测存储器单元的编程结果。 根据存储单元的编程结果调整施加在存储单元上的编程电压。 还提供闪存。