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公开(公告)号：US20080055958A1
公开(公告)日：2008-03-06
申请号：US11976531
申请日：2007-10-25
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。
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公开(公告)号：US20090262574A1
公开(公告)日：2009-10-22
申请号：US12427392
申请日：2009-04-21
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译： 实现了高可靠性的大容量相变存储器模块。 根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件 其中所选择的存储器单元被定位。 根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件） 电路和电流镜电路。
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公开(公告)号：US20110216583A1
公开(公告)日：2011-09-08
申请号：US13112567
申请日：2011-05-20
申请人： Satoru HANZAWA , Hitoshi Kume
发明人： Satoru HANZAWA , Hitoshi Kume
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0083 , G11C2213/71 , G11C2213/72
摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.
摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。
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公开(公告)号：US20100315895A1
公开(公告)日：2010-12-16
申请号：US12862350
申请日：2010-08-24
申请人： Satoru HANZAWA , Takeshi Sakata
发明人： Satoru HANZAWA , Takeshi Sakata
IPC分类号： G11C7/00
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。
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公开(公告)号：US20090168505A1
公开(公告)日：2009-07-02
申请号：US12335418
申请日：2008-12-15
申请人： Satoru HANZAWA , Hitoshi Kume
发明人： Satoru HANZAWA , Hitoshi Kume
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0083 , G11C2213/71 , G11C2213/72
摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.
摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。
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公开(公告)号：US20120155162A1
公开(公告)日：2012-06-21
申请号：US13327585
申请日：2011-12-15
申请人： Satoru HANZAWA
发明人： Satoru HANZAWA
CPC分类号： G11C7/22 , G11C7/1039 , G11C7/1042 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2207/2209 , G11C2207/2245 , G11C2211/5623 , G11C2211/5624
摘要： A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.
摘要翻译： 半导体存储装置提供具有高速运行，低电流和高可靠性的大容量相变存储器。 在存储器区域控制电路中激活读出启动信号的期间，并且读出驱动器对的块在上部存储区域中进行验证读取; 激活存储器区域控制电路中的写入使能信号，并且读出锁存器和写入驱动器对的块对下部存储器区域中的数据执行重写操作。 这种类型的操作允许通过在一个存储器区域中执行验证读取同时在其他存储器区域中执行时分重写来消除验证读取所需的时间和时分写入操作所需的时间，以实现更高的 可靠性重写操作以及抑制重写操作峰值电流。
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公开(公告)号：US20110013447A1
公开(公告)日：2011-01-20
申请号：US12890636
申请日：2010-09-25
申请人： Satoru HANZAWA , Hitoshi Kume
发明人： Satoru HANZAWA , Hitoshi Kume
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0083 , G11C2213/71 , G11C2213/72
摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.
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公开(公告)号：US20080089137A1
公开(公告)日：2008-04-17
申请号：US11873254
申请日：2007-10-16
申请人： Satoru HANZAWA , Takeshi Sakata
发明人： Satoru HANZAWA , Takeshi Sakata
IPC分类号： G11C7/10
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。
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公开(公告)号：US20100058127A1
公开(公告)日：2010-03-04
申请号：US12469778
申请日：2009-05-21
申请人： Motoyasu TERAO , Satoru HANZAWA , Hitoshi KUME , Minoru OGUSHI , Yoshitaka SASAGO , Masaharu KINOSHITA , Norikatsu TAKAURA
发明人： Motoyasu TERAO , Satoru HANZAWA , Hitoshi KUME , Minoru OGUSHI , Yoshitaka SASAGO , Masaharu KINOSHITA , Norikatsu TAKAURA
IPC分类号： G06F11/26
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译： 为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域 第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。 控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。 存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。
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公开(公告)号：US20120075926A1
公开(公告)日：2012-03-29
申请号：US13312620
申请日：2011-12-06
申请人： Satoru HANZAWA , Hitoshi Kume
发明人： Satoru HANZAWA , Hitoshi Kume
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0026 , G11C13/0069 , G11C2013/0076 , G11C2013/0078 , G11C2013/0083 , G11C2213/71 , G11C2213/72
摘要： A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.
摘要翻译： 提供了具有高度可靠的操作的相变存储器。 半导体器件具有存储器阵列，其具有使用硫族化物材料和二极管层叠存储层的存储单元的结构，并且根据所选择的存储单元所在的层来改变初始化条件和写入条件。 初始化条件和写入条件（这里是复位条件）根据操作通过根据操作选择电流镜电路和通过电压选择电路和电流镜电路中的复位电流的控制机构而改变。
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