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    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
    3.
    发明申请
    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow 有权
    具有应变通道区域和集成应变CMOS流的非平面pMOS结构

    公开(公告)号：US20080169512A1

    公开(公告)日：2008-07-17

    申请号：US12004706

    申请日：2007-12-20

    申请人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy M. Zelick ,  Robert Chau

    发明人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy M. Zelick ,  Robert Chau

    IPC分类号： H01L29/737 ,  H01L21/8238

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785 ,  H01L29/78687 ,  Y10S438/933

    摘要： A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

    摘要翻译： 描述了具有应变通道区域和非平面三栅极集成应变互补金属氧化物半导体（CMOS）结构的非平面三栅极p-MOS晶体管结构。 在隔离硅绝缘体（SOI）衬底上形成松弛的Si 1-x Ge层。 将轻松的Si 1-x N Ge x层图案化并随后蚀刻以在氧化物上形成翅片。 在弛豫的Si 1-x N层中Ge含量y高于Ge含量x的压应力Si 1-y Ge层， Ge层是在翅片上外延生长的。 Si 1-y Ge 3层覆盖翅片的顶部和两个侧壁。 Si 1-y Ge层中的压应力基本上增加了非平面三栅极p-MOS晶体管结构的沟道中的空穴迁移率。

    Non-planar MOS structure with a strained channel region
    6.
    发明授权
    Non-planar MOS structure with a strained channel region 有权
    具有应变通道区域的非平面MOS结构

    公开(公告)号：US07531393B2

    公开(公告)日：2009-05-12

    申请号：US11373776

    申请日：2006-03-09

    申请人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Robert Chau

    发明人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Robert Chau

    IPC分类号： H01L21/84

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    摘要： An embodiment is a non-planar MOS transistor structure including a strained channel region. The combination of a non-planar MOS transistor structure, and in particular an NMOS tri-gate transistor, with the benefits of a strained channel yields improved transistor drive current, switching speed, and decreased leakage current for a given gate length width versus a non-planar MOS structure with an unstrained channel or planar MOS structure including a strained channel.

    摘要翻译： 一个实施例是包括应变通道区域的非平面MOS晶体管结构。 具有应变通道优点的非平面MOS晶体管结构，特别是NMOS三栅极晶体管的组合产生了对于给定栅极长度宽度相对于非晶体管的晶体管驱动电流，开关速度和降低的漏电流 具有包含应变通道的无约束通道或平面MOS结构的平面MOS结构。

    Tri-gate transistors and methods to fabricate same
    7.
    发明授权
    Tri-gate transistors and methods to fabricate same 有权
    三栅晶体管及其制造方法

    公开(公告)号：US07268058B2

    公开(公告)日：2007-09-11

    申请号：US10760028

    申请日：2004-01-16

    申请人： Robert Chau ,  Suman Datta ,  Brian S Doyle ,  Been-Yih Jin

    发明人： Robert Chau ,  Suman Datta ,  Brian S Doyle ,  Been-Yih Jin

    IPC分类号： H01L21/76

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

    摘要翻译： 本发明的实施例提供了一种用于对绝缘体上硅晶体管制造实现均匀的硅体高度的方法。 对于一个实施例，牺牲氧化物层设置在半导体衬底上。 氧化层被蚀刻以形成沟槽。 然后用半导体材料填充沟槽。 然后将半导体材料与氧化物层的其余部分平坦化，然后除去氧化物层的其余部分。 这样暴露的半导体鳍片具有均匀的高度，在规定的公差范围内。

    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
    10.
    发明授权
    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow 有权
    具有应变通道区域和集成应变CMOS流的非平面pMOS结构

    公开(公告)号：US07348284B2

    公开(公告)日：2008-03-25

    申请号：US10915780

    申请日：2004-08-10

    申请人： Brian S Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy M Zelick ,  Robert Chau

    发明人： Brian S Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy M Zelick ,  Robert Chau

    IPC分类号： H01L21/00

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785 ,  H01L29/78687 ,  Y10S438/933

    摘要： A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-xGex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

    摘要翻译： 描述了具有应变通道区域和非平面三栅极集成应变互补金属氧化物半导体（CMOS）结构的非平面三栅极p-MOS晶体管结构。 在隔离硅绝缘体（SOI）衬底上形成松弛的Si 1-x Ge层。 将轻松的Si 1-x N Ge x层图案化并随后蚀刻以在氧化物上形成翅片。 在弛豫的Si 1-x N层中Ge含量y高于Ge含量x的压应力Si 1-y Ge层， Ge层是在翅片上外延生长的。 Si 1-y Ge 3层覆盖翅片的顶部和两个侧壁。 Si 1-y Ge层中的压应力基本上增加了非平面三栅极p-MOS晶体管结构的沟道中的空穴迁移率。