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    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
    1.
    发明申请
    Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow 有权
    具有应变通道区域和集成应变CMOS流的非平面pMOS结构

    公开(公告)号：US20080169512A1

    公开(公告)日：2008-07-17

    申请号：US12004706

    申请日：2007-12-20

    申请人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy M. Zelick ,  Robert Chau

    发明人： Brian S. Doyle ,  Suman Datta ,  Been-Yih Jin ,  Nancy M. Zelick ,  Robert Chau

    IPC分类号： H01L29/737 ,  H01L21/8238

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785 ,  H01L29/78687 ,  Y10S438/933

    摘要： A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.

    摘要翻译： 描述了具有应变通道区域和非平面三栅极集成应变互补金属氧化物半导体（CMOS）结构的非平面三栅极p-MOS晶体管结构。 在隔离硅绝缘体（SOI）衬底上形成松弛的Si 1-x Ge层。 将轻松的Si 1-x N Ge x层图案化并随后蚀刻以在氧化物上形成翅片。 在弛豫的Si 1-x N层中Ge含量y高于Ge含量x的压应力Si 1-y Ge层， Ge层是在翅片上外延生长的。 Si 1-y Ge 3层覆盖翅片的顶部和两个侧壁。 Si 1-y Ge层中的压应力基本上增加了非平面三栅极p-MOS晶体管结构的沟道中的空穴迁移率。

    Two-dimensional condensation for uniaxially strained semiconductor fins
    2.
    发明授权
    Two-dimensional condensation for uniaxially strained semiconductor fins 有权
    用于单轴应变半导体翅片的二维冷凝

    公开(公告)号：US08211772B2

    公开(公告)日：2012-07-03

    申请号：US12646427

    申请日：2009-12-23

    申请人： Jack T. Kavalieros ,  Nancy M. Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

    发明人： Jack T. Kavalieros ,  Nancy M. Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

    IPC分类号： H01L21/336

    CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

    摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

    摘要翻译： 公开了用于实现半导体翅片的多面冷凝的技术。 这些技术可以用于例如制造基于鳍的晶体管。 在一个示例的情况下，在体基板上设置应变层。 应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。 在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。 将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。