公开(公告)号：US20060267107A1

公开(公告)日：2006-11-30

申请号：US11252493

申请日：2005-10-17

申请人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

发明人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/28518

摘要： A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

摘要翻译： 提供集成电路的结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

公开(公告)号：US20050006705A1

公开(公告)日：2005-01-13

申请号：US10615086

申请日：2003-07-07

申请人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

发明人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L21/28518

摘要： A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform silicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

摘要翻译： 提供一种集成电路的形成方法和结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

公开(公告)号：US20050153496A1

公开(公告)日：2005-07-14

申请号：US10756023

申请日：2004-01-12

申请人： Minh Ngo ,  Simon Chan ,  Paul Besser ,  Paul King ,  Errol Ryan ,  Robert Chiu

发明人： Minh Ngo ,  Simon Chan ,  Paul Besser ,  Paul King ,  Errol Ryan ,  Robert Chiu

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/6659 ,  H01L29/665

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

公开(公告)号：US20060267087A1

公开(公告)日：2006-11-30

申请号：US11229188

申请日：2005-09-15

申请人： Robert Chiu ,  Paul Besser ,  Simon Chan ,  Jeffrey Patton ,  Austin Frenkel ,  Thorsten Kammler ,  Errol Ryan

发明人： Robert Chiu ,  Paul Besser ,  Simon Chan ,  Jeffrey Patton ,  Austin Frenkel ,  Thorsten Kammler ,  Errol Ryan

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

摘要翻译： 提供集成电路。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。 底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。 底部和顶部的硅化物金属形成它们的自杀剂。 介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

公开(公告)号：US07378310B1

公开(公告)日：2008-05-27

申请号：US11116551

申请日：2005-04-27

申请人： Connie Pin-Chin Wang ,  Zoran Krivokapic ,  Suzette Keefe Pangrle ,  Robert Chiu ,  Lu You

发明人： Connie Pin-Chin Wang ,  Zoran Krivokapic ,  Suzette Keefe Pangrle ,  Robert Chiu ,  Lu You

IPC分类号： H01L21/8242

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881

摘要： A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

摘要翻译： 一种具有金属纳米晶电荷存储结构的存储器件的制造方法。 提供衬底并且在衬底上生长第一介电材料层。 在第一绝缘材料层上形成具有第一形成热的金属氧化物层。 在金属氧化物层上形成具有第二次形成热的金属层。 第二次形成的热量大于第一次形成的热量。 金属氧化物层和金属层被退火，这导致金属层将金属氧化物层还原成金属形式，然后使其聚集形成金属岛。 金属层变得氧化，从而将金属岛嵌入氧化物层中以形成纳米晶层。 在纳米晶体层上形成控制氧化物，在控制氧化物上形成栅电极。

公开(公告)号：US20080131940A1

公开(公告)日：2008-06-05

申请号：US11570423

申请日：2005-06-22

申请人： Robert Chiu ,  Jun Song

发明人： Robert Chiu ,  Jun Song

IPC分类号： C12P19/34 ,  C07H21/02 ,  C12N15/63 ,  C12N5/00 ,  C12N15/87

CPC分类号： C12N15/1132 ,  C12N15/111 ,  C12N2310/111 ,  C12N2310/14 ,  C12N2320/32 ,  C12N2830/008 ,  C12N2830/85

摘要： The present invention provides nucleic acids that include a nucleotide sequence that encodes an siRNA, which nucleotide sequence is operably linked to a target cell-specific promoter RNA polymerase II promoter. The present invention further provides vectors, including expression vectors, which include a subject nucleic acid; and host cells that harbor a subject nucleic acid or a subject expression vector. The present invention further provides methods of modulating (e.g., reducing) expression of a gene in a target cell-specific manner, the methods generally involving introducing into a cell a subject expression vector.

摘要翻译： 本发明提供核酸，其包括编码siRNA的核苷酸序列，该核苷酸序列可操作地连接到靶细胞特异性启动子RNA聚合酶II启动子。 本发明还提供了包括表达载体的载体，其包括受试核酸; 和携带受试者核酸或受试者表达载体的宿主细胞。 本发明还提供了以目标细胞特异性方式调节（例如，降低）基因表达的方法，所述方法通常涉及向细胞中引入受试者表达载体。

公开(公告)号：US06216686B1

公开(公告)日：2001-04-17

申请号：US09602062

申请日：2000-06-23

申请人： Robert Chiu

发明人： Robert Chiu

IPC分类号： F24C1520

CPC分类号： F24C15/20

摘要： A range hood includes a motor housing having two slanted motor supporting platforms provided thereon wherein two motor are detachably mounted on the two slanted motor supporting platforms respectively such that the motors are inclined with respect to a ceiling of a casing. A drag area provided by the inclined motor arrangement is highly increased in order cover the entire cooking surface. Furthermore, all parts of the range hood are adapted to be assembled and disassembled without using tools such that a user is able to easily clean up the range hood part by part in which the parts made of durable material are dishwasher-safe so as to easily maintain the range hood for better performance.

摘要翻译： 抽油烟机包括具有设置在其上的两个倾斜的电动机支撑平台的电动机壳体，其中两个电动机分别可拆卸地安装在两个倾斜的电动机支撑平台上，使得电动机相对于壳体的天花板倾斜。 由倾斜电动机装置提供的阻力区域以覆盖整个烹饪表面的顺序高度增加。 此外，抽油烟机的所有部件都适于在不使用工具的情况下进行组装和拆卸，使得用户能够容易地清洁抽油烟机部分，部分地由耐用材料制成的零件是洗碗机安全的，以便容易地 保持抽油烟机的性能更好。

公开(公告)号：US09299643B2

公开(公告)日：2016-03-29

申请号：US12286149

申请日：2008-09-29

申请人： Zheng Wang ,  Connie Wang ,  Erik Wilson ,  Wen Yu ,  Robert Chiu

发明人： Zheng Wang ,  Connie Wang ,  Erik Wilson ,  Wen Yu ,  Robert Chiu

IPC分类号： H01L29/40 ,  H01L23/485 ,  H01L21/768 ,  H01L23/532 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L23/485 ,  H01L21/76877 ,  H01L23/53252 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

摘要翻译： 导电互连通过介电层中的开口设置，电连接两个导电层。 在一个实施例中，互连由完全填充介电层中的开口的钌形成。 在另一个实施方案中，在提供钌之前，在开口中提供钛的粘附层。 在使用这种方法时，可实现20:1或更大的纵横比（互连长度与其宽度之比）。

公开(公告)号：US07948292B1

公开(公告)日：2011-05-24

申请号：US12133697

申请日：2008-06-05

申请人： Robert Chiu ,  Denitza Tchoevska ,  Parissa Najdesamii ,  Mark H. Sternberg

发明人： Robert Chiu ,  Denitza Tchoevska ,  Parissa Najdesamii ,  Mark H. Sternberg

IPC分类号： H03L5/00

CPC分类号： H03K19/0008 ,  H01L27/0207 ,  H01L27/11898

摘要： An integrated circuit includes first and second voltage domains. The first voltage domain is associated with a positive voltage supply grid and the second voltage domain is associated with a selectably on voltage supply grid. A switch is used to selectably switch on and off the selectably on voltage supply grid to power the second voltage domain. A buffer cell cluster of at least on initial buffer cell and a pair of insulator cells is coupled to the positive voltage supply grid electrically independent of the nodes of a switch and is capable of buffering a feed-through signal having a logic one voltage level defined substantially at the voltage level of the positive voltage supply grid. The buffer cell cluster has two distal ends. buffer cell cluster, at one distal end, is coupled to a first insulator cell of the pair of cells while, at the other distal end, the buffer cell cluster is coupled to a second insulator cell of the pair of the cells.

摘要翻译： 集成电路包括第一和第二电压域。 第一电压域与正电压电网相关联，并且第二电压域与可选择的上电压电网相关联。 开关用于选择性地打开和关闭可选择的电压电网以为第二电压域供电。 至少在初始缓冲器单元和一对绝缘体单元上的缓冲单元簇与电压独立于开关节点的正电压电网连接，并且能够缓冲具有定义的逻辑1电压电平的馈通信号 基本上处于正电压电网的电压电平。 缓冲细胞簇具有两个远端。 在一个远端处的缓冲细胞簇耦合到所述一对细胞的第一绝缘体细胞，而在另一远端处，所述缓冲细胞簇耦合到所述一对细胞的第二绝缘体细胞。

公开(公告)号：US20100078815A1

公开(公告)日：2010-04-01

申请号：US12286149

申请日：2008-09-29

申请人： Zheng Wang ,  Connie Wang ,  Erik Wilson ,  Wen Yu ,  Robert Chiu

发明人： Zheng Wang ,  Connie Wang ,  Erik Wilson ,  Wen Yu ,  Robert Chiu

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/485 ,  H01L21/76877 ,  H01L23/53252 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically conductive interconnect is provided through an opening in a dielectric layer, electrically connecting two conductive layers. In one embodiment, the interconnect is formed by ruthenium entirely filling the opening in the dielectric layer. In another embodiment, an adhesion layer of titanium is provided in the opening prior to providing the ruthenium. In using this approach, an aspect ratio (i.e., the ratio of the length of the interconnect to the width thereof) of 20:1 or greater is achievable.

摘要翻译： 导电互连通过介电层中的开口设置，电连接两个导电层。 在一个实施例中，互连由完全填充介电层中的开口的钌形成。 在另一个实施方案中，在提供钌之前，在开口中提供钛的粘附层。 在使用这种方法时，可实现20:1或更大的纵横比（互连长度与其宽度之比）。