-
公开(公告)号：US06555858B1
公开(公告)日：2003-04-29
申请号：US09713734
申请日：2000-11-15
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00
摘要： A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (250), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.
摘要翻译： 公开了一种用于磁存储元件（240a）的自对准磁性覆层位线结构（274）及其形成方法，其中自对准磁性覆层位线结构（274）在沟槽（258）内延伸并且包括 导电材料（250），磁性覆层侧壁（262）和磁性覆层帽（252）。 至少部分地围绕导电材料（264）的磁性覆层侧壁（262）和磁性覆层帽（252）相对于沟槽的顶部基本上在沟槽内凹陷。
-
公开(公告)号：US06916669B2
公开(公告)日：2005-07-12
申请号：US10378348
申请日：2003-03-03
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/22 , H01L43/08 , H01L21/00 , H01L21/20
CPC分类号： H01L27/228 , B82Y10/00
摘要： A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.
摘要翻译： 公开了一种用于磁存储元件（240a）的自对准磁性覆层位线结构（274）及其形成方法，其中自对准磁性覆层位线结构（274）在沟槽（258）内延伸，并且 包括导电材料（264），磁性覆层侧壁（262）和磁性覆层帽（252）。 至少部分地围绕导电材料（264）的磁性包覆侧壁（262）和磁性包覆帽（252）相对于沟槽的顶部基本上在沟槽内凹陷。
-
公开(公告)号：US07751177B2
公开(公告)日：2010-07-06
申请号：US12431288
申请日：2009-04-28
IPC分类号： H01G4/06
摘要： A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.
摘要翻译： 一种形成电容器的方法包括提供含金属的底部电极，在含金属的底部电极上形成电容器绝缘体，在电容器绝缘体之上形成含金属的顶部电极，并在 电容器绝缘体并且至少部分地围绕含金属的顶部电极。 形成含电介质的场改性层可以包括氧化含金属的场改性层的侧壁。 在形成含金属的顶部电极之前，可以在电容器绝缘体之上形成阻挡层。
-
4.发明授权Thin-film capacitor with a field modification layer and methods for forming the same 有权具有场改性层的薄膜电容器及其形成方法公开(公告)号：US07534693B2
公开(公告)日：2009-05-19
申请号：US11326524
申请日：2006-01-04
IPC分类号： H01L21/20
摘要： A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.
摘要翻译： 一种形成电容器的方法包括提供含金属的底部电极，在含金属的底部电极上形成电容器绝缘体，在电容器绝缘体之上形成含金属的顶部电极，并在 电容器绝缘体并且至少部分地围绕含金属的顶部电极。 形成含电介质的场改性层可以包括氧化含金属的场改性层的侧壁。 在形成含金属的顶部电极之前，可以在电容器绝缘体之上形成阻挡层。
-
公开(公告)号：US08415212B2
公开(公告)日：2013-04-09
申请号：US12721738
申请日：2010-03-11
申请人： James K. Schaeffer , Eric D. Luckowski , Todd C. Bailey , Amy L. Child , Daniel Jaeger , Renee Mo , Ying H. Tsang
发明人： James K. Schaeffer , Eric D. Luckowski , Todd C. Bailey , Amy L. Child , Daniel Jaeger , Renee Mo , Ying H. Tsang
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/3105 , H01L21/31138 , H01L21/31144 , H01L21/823842 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/66651
摘要： A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.
摘要翻译： 描述了一种用于在至少NMOS器件区域中具有稀土氧化物覆盖层（44）的高k栅介质层（32）之上制造金属栅电极（85,86）的方法和装置， 具有无氧等离子体工艺（42）的稀土氧化物覆盖层（44）以改善光致抗蚀剂的粘合性，在稀土氧化物覆盖层（44）上直接形成图案化的光致抗蚀剂层（52），然后施加湿蚀刻工艺 （62）从PMOS器件区域去除所述稀土氧化物覆盖层（44）的暴露部分。
-
公开(公告)号：US06790719B1
公开(公告)日：2004-09-14
申请号：US10410043
申请日：2003-04-09
IPC分类号： H01L21337
CPC分类号： H01L21/823468 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻来蚀刻N沟道栅极堆叠和P沟道栅极堆叠的一部分。 通过湿式蚀刻完成P沟道栅叠层的蚀刻。 湿蚀刻对栅极电介质和第二金属类型是非常选择的，使得N沟道晶体管不会通过完成P沟道栅极堆叠的蚀刻而受到不利影响。
-
公开(公告)号：US20090279226A1
公开(公告)日：2009-11-12
申请号：US12431288
申请日：2009-04-28
摘要： A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.
摘要翻译： 一种形成电容器的方法包括提供含金属的底部电极，在含金属的底部电极上形成电容器绝缘体，在电容器绝缘体之上形成含金属的顶部电极，并在 电容器绝缘体并且至少部分地围绕含金属的顶部电极。 形成含电介质的场改性层可以包括氧化含金属的场改性层的侧壁。 在形成含金属的顶部电极之前，可以在电容器绝缘体之上形成阻挡层。
-
公开(公告)号：US20110223756A1
公开(公告)日：2011-09-15
申请号：US12721738
申请日：2010-03-11
申请人： James K. Schaeffer , Eric D. Luckowski , Todd C. Bailey , Amy L. Child , Daniel Jaeger , Renee Mo , Ying H. Tsang
发明人： James K. Schaeffer , Eric D. Luckowski , Todd C. Bailey , Amy L. Child , Daniel Jaeger , Renee Mo , Ying H. Tsang
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/3105 , H01L21/31138 , H01L21/31144 , H01L21/823842 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/66651
摘要： A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.
摘要翻译： 描述了一种用于在至少NMOS器件区域中具有稀土氧化物覆盖层（44）的高k栅介质层（32）之上制造金属栅电极（85,86）的方法和装置， 具有无氧等离子体工艺（42）的稀土氧化物覆盖层（44）以改善光致抗蚀剂的粘合性，在稀土氧化物覆盖层（44）上直接形成图案化的光致抗蚀剂层（52），然后施加湿蚀刻工艺 （62）从PMOS器件区域去除所述稀土氧化物覆盖层（44）的暴露部分。
-
公开(公告)号：US08309419B2
公开(公告)日：2012-11-13
申请号：US12365317
申请日：2009-02-04
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.
摘要翻译： 描述了用于在高k栅极电介质层（31,32）上制造单个金属栅极（35,36）的方法和装置，其通过形成第一封盖而分别地掺杂在PMOS和NMOS器件区域（96,97）中 至少在NMOS器件区域中的高k栅极电介质层（22）上具有第一掺杂剂物质的氧化物层（23），并且还在高k栅极电介质上形成具有第二掺杂物种类的第二覆盖氧化物层（27） 至少PMOS器件区域中的第二层（22），其中第一和第二掺杂物种类扩散到栅介质层（22）中，以在高k栅极的PMOS器件区域中形成第一固定电荷层（31） 电介质区域和在高k栅极电介质区域的NMOS器件区域中的第二固定电荷层（32）。
-
公开(公告)号：US20100197128A1
公开(公告)日：2010-08-05
申请号：US12365317
申请日：2009-02-04
IPC分类号： H01L21/283 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.
摘要翻译： 描述了用于在高k栅极电介质层（31,32）上制造单个金属栅极（35,36）的方法和装置，其通过形成第一封盖而分别地掺杂在PMOS和NMOS器件区域（96,97）中 至少在NMOS器件区域中的高k栅极电介质层（22）上具有第一掺杂剂物质的氧化物层（23），并且还在高k栅极电介质上形成具有第二掺杂物种类的第二覆盖氧化物层（27） 至少PMOS器件区域中的第二层（22），其中第一和第二掺杂物种类扩散到栅介质层（22）中，以在高k栅极的PMOS器件区域中形成第一固定电荷层（31） 电介质区域和在高k栅极电介质区域的NMOS器件区域中的第二固定电荷层（32）。
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.024 秒)
