公开(公告)号：US20140075441A1

公开(公告)日：2014-03-13

申请号：US13615416

申请日：2012-09-13

申请人： Robert J. Blainey ,  Harold W. Cain ,  Susan E. Eisen ,  Bradly G. Frey ,  Charles B. Hall ,  Hung Q. Le ,  Cathy May

发明人： Robert J. Blainey ,  Harold W. Cain ,  Susan E. Eisen ,  Bradly G. Frey ,  Charles B. Hall ,  Hung Q. Le ,  Cathy May

IPC分类号： G06F9/46

CPC分类号： G06F9/467 ,  G06F11/1474 ,  G06F11/36 ,  G06F11/3648

摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

摘要翻译： 处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。 事务存储器存储由处理器核心执行的多个事务的信息。 处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。 然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

公开(公告)号：US09268598B2

公开(公告)日：2016-02-23

申请号：US13615416

申请日：2012-09-13

申请人： Robert J. Blainey ,  Harold W. Cain ,  Susan E. Eisen ,  Bradly G. Frey ,  Charles B. Hall ,  Hung Q. Le ,  Cathy May

发明人： Robert J. Blainey ,  Harold W. Cain ,  Susan E. Eisen ,  Bradly G. Frey ,  Charles B. Hall ,  Hung Q. Le ,  Cathy May

IPC分类号： G06F9/46 ,  G06F11/14 ,  G06F11/36

CPC分类号： G06F9/467 ,  G06F11/1474 ,  G06F11/36 ,  G06F11/3648

摘要： A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

摘要翻译： 处理器核心包括事务存储器，事务失败指令地址寄存器（TFIAR）和事务故障数据地址寄存器（TFDAR）。 事务存储器存储由处理器核心执行的多个事务的信息。 处理器核心分别从TFIAR和TFDAR检索与中止事务相关联的指令和数据地址，并将它们存储到一个概要分析表中。 然后，处理器核心基于与中止事务相关联的指令和数据地址生成分析信息。

公开(公告)号：US09626187B2

公开(公告)日：2017-04-18

申请号：US12788351

申请日：2010-05-27

申请人： Harold W. Cain, III ,  Bradly G. Frey ,  Benjamin Herrenschmidt ,  Hung Q. Le ,  Cathy May ,  Maged M. Michael ,  Jose E. Moreira ,  Priya A. Nagpurkar ,  Naresh Nayar ,  Randal C. Swanberg

发明人： Harold W. Cain, III ,  Bradly G. Frey ,  Benjamin Herrenschmidt ,  Hung Q. Le ,  Cathy May ,  Maged M. Michael ,  Jose E. Moreira ,  Priya A. Nagpurkar ,  Naresh Nayar ,  Randal C. Swanberg

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/30 ,  G06F9/46 ,  G06F9/38

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/467

摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

公开(公告)号：US20110296148A1

公开(公告)日：2011-12-01

申请号：US12788351

申请日：2010-05-27

申请人： Harold W. Cain, III ,  Bradly G. Frey ,  Benjamin Herrenschmidt ,  Hung Q. Le ,  Cathy May ,  Maged M. Michael ,  Jose E. Moreira ,  Priya A. Nagpurkar ,  Naresh Nayar ,  Randal C. Swanberg

发明人： Harold W. Cain, III ,  Bradly G. Frey ,  Benjamin Herrenschmidt ,  Hung Q. Le ,  Cathy May ,  Maged M. Michael ,  Jose E. Moreira ,  Priya A. Nagpurkar ,  Naresh Nayar ,  Randal C. Swanberg

IPC分类号： G06F9/312

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/467

摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

摘要翻译： 在具有处理器和事务存储器的数据处理系统中提供用于在数据处理系统中执行事务的机制。 这些机制执行包括修改事务存储器的至少一部分的一个或多个指令的事务。 响应于由处理器执行的事务挂起指令，事务被暂停。 当事务被暂停时，暂停的代码块以非事务方式执行。 确定在事务中止时是否发生中断。 响应于在事务中止时发生的中断，事务中止操作被延迟，直到事务中止停止为止。

公开(公告)号：US20130013899A1

公开(公告)日：2013-01-10

申请号：US13176833

申请日：2011-07-06

申请人： Christopher M. Barton ,  Harold W. Cain, III ,  Bradly G. Frey ,  Hung Q. Le ,  Maged M. Michael ,  Raul E. Silvera ,  Derek E. Williams ,  Michael Wong ,  Peng Wu

发明人： Christopher M. Barton ,  Harold W. Cain, III ,  Bradly G. Frey ,  Hung Q. Le ,  Maged M. Michael ,  Raul E. Silvera ,  Derek E. Williams ,  Michael Wong ,  Peng Wu

IPC分类号： G06F9/30

CPC分类号： G06F9/466

摘要： Mechanisms are provided for performing escape actions within transactions. These mechanisms execute a transaction comprising a transactional section and an escape action. The transactional section is comprised of one or more instructions that are to be executed in an atomic manner as part of the transaction. The escape action is comprised of one or more instructions to be executed in a non-transactional manner. These mechanisms further populate at least one actions list data structure, associated with a thread of the data processing system that is executing the transaction, with one or more actions associated with the escape action. Moreover, these mechanisms execute one or more actions in the actions list data structure based upon whether the transaction commits successfully or is aborted.

摘要翻译： 提供了在事务中执行转义操作的机制。 这些机制执行包括事务部分和转义动作的事务。 事务部分由作为事务的一部分以原子方式执行的一个或多个指令组成。 转义动作由以非事务方式执行的一个或多个指令组成。 这些机制进一步填充与执行交易的数据处理系统的线程相关联的至少一个动作列表数据结构，其中一个或多个动作与转义动作相关联。 此外，这些机制基于事务提交成功还是中止，在动作列表数据结构中执行一个或多个动作。

公开(公告)号：US08544022B2

公开(公告)日：2013-09-24

申请号：US13465115

申请日：2012-05-07

申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F11/00 ,  G06F13/24

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

摘要翻译： 提供了在数据处理系统中执行事务的机制。 在处理器的内部寄存器中生成事务检查点数据结构。 事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。 执行包括由处理器执行的代码的第一部分的事务。 在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。 然后执行第二部分代码。 响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

公开(公告)号：US08424015B2

公开(公告)日：2013-04-16

申请号：US12894308

申请日：2010-09-30

申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F11/00 ,  G06F13/24

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

公开(公告)号：US20120246658A1

公开(公告)日：2012-09-27

申请号：US13465115

申请日：2012-05-07

申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

IPC分类号： G06F9/46

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

公开(公告)号：US20120084477A1

公开(公告)日：2012-04-05

申请号：US12894308

申请日：2010-09-30

申请人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

发明人： Richard L. Arndt ,  Harold W. Cain, III ,  Bradly G. Frey ,  Cathy May

IPC分类号： G06F13/24

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

摘要： Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

摘要翻译： 提供了在数据处理系统中执行事务的机制。 在处理器的内部寄存器中生成事务检查点数据结构。 事务检查点数据结构存储表示执行相应事务之前的时间的程序寄存器的状态的事务检查点数据。 执行包括由处理器执行的代码的第一部分的事务。 在执行事务时接收事务的中断，结果，事务检查点数据被存储到数据处理系统的存储器中的数据结构。 然后执行第二部分代码。 响应于发生的事件导致处理器的执行切换返回到事务的执行，使用数据处理系统的存储器中的数据结构恢复程序寄存器的状态。

公开(公告)号：US09047079B2

公开(公告)日：2015-06-02

申请号：US13435123

申请日：2012-03-30

申请人： Becky Bruce ,  Giles R. Frazier ,  Bradly G. Frey ,  Kumar K. Gala ,  Cathy May ,  Michael D. Snyder ,  Gary Whisenhunt ,  James Xenidis

发明人： Becky Bruce ,  Giles R. Frazier ,  Bradly G. Frey ,  Kumar K. Gala ,  Cathy May ,  Michael D. Snyder ,  Gary Whisenhunt ,  James Xenidis

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30101 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3889

摘要： A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

摘要翻译： 用于指示关于被禁用线程的安全共享资源状况的技术提供了一种用于向其他硬件线程提供快速指示的机制，临时禁用的线程不再影响共享资源，例如共享专用寄存器和翻译查找， 处理器核心内的缓冲区。 来自核心内的流水线的信号表示流水线中的任何待执行的任何指示是否影响共享资源，如果没有，则通过线程状态寄存器中的状态更改将线程禁用状态呈现给其他线程。 在接收到特定硬件线程被禁用的指示时，控制逻辑停止对特定硬件线程的指令的分派，然后等待直到由指令影响共享资源的任何指示已经被清除。 然后控制逻辑更新线程状态以指示线程被禁用。