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公开(公告)号：US07070686B2
公开(公告)日：2006-07-04
申请号：US10274755
申请日：2002-10-21
CPC分类号： C25D5/006 , C25D7/123 , C25D17/001 , C25D17/008 , C25D17/06
摘要： In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.
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2.发明授权公开(公告)号：US06514393B1
公开(公告)日：2003-02-04
申请号：US09542890
申请日：2000-04-04
IPC分类号： C25C1704
CPC分类号： C25D7/12 , C25D7/123 , C25D17/001 , C25D17/06
摘要： An electrochemical reactor is used to electrofill damascene architecture for integrated circuits or for electropolishing magnetic disks. An inflatable bladder is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The bladder establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.
摘要翻译： 电化学反应器用于对集成电路或电解抛光磁盘的大马士革结构进行电解填充。 在电镀操作期间使用可膨胀的气囊来屏蔽所施加的磁场，以补偿沿着晶片半径的电位降。 膀胱在电解液中产生反向电位降，以克服晶片上的铜薄膜晶种层的电阻。
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3.发明授权Method and apparatus for spatially uniform electropolishing and electrolytic etching 失效用于空间均匀电解和电解蚀刻的方法和装置
公开(公告)号：US5096550A
公开(公告)日：1992-03-17
申请号：US597225
申请日：1990-10-15
CPC分类号： C25F7/00 , C25F3/02 , C25F3/16 , Y10S204/07
摘要： In an electropolishing or electrolytic etching apparatus the anode is separated from the cathode to prevent bubble transport to the anode and to produce a uniform current distribution at the anode by means of a solid nonconducting anode-cathode barrier. The anode extends into the top of the barrier and the cathode is outside the barrier. A virtual cathode hole formed in the bottom of the barrier below the level of the cathode permits current flow while preventing bubble transport. The anode is rotatable and oriented horizontally facing down. An extended anode is formed by mounting the workpiece in a holder which extends the electropolishing or etching area beyond the edge of the workpiece to reduce edge effects at the workpiece. A reference electrode controls cell voltage. Endpoint detection and current shut-off stop polishing. Spatially uniform polishing or etching can be rapidly performed.
摘要翻译： 在电解抛光或电解蚀刻装置中，阳极与阴极分离，以防止气泡传输到阳极，并通过固体非导电阳极 - 阴极屏障在阳极处产生均匀的电流分布。 阳极延伸到屏障的顶部，阴极在屏障外。 形成在阴极底部的阴极底部的虚拟阴极孔允许电流流动，同时防止气泡输送。 阳极可旋转并水平定向朝下。 扩展阳极通过将工件安装在将电解抛光或蚀刻区域延伸超过工件边缘的保持器中形成，以减少工件的边缘效应。 参考电极控制电池电压。 端点检测和电流切断停止抛光。 可以快速进行空间均匀的抛光或蚀刻。
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4.发明授权Electroplanarization of large and small damascene features using diffusion barriers and electropolishing 有权使用扩散屏障和电解抛光的大型和小型镶嵌特征的电平面化公开(公告)号：US06315883B1
公开(公告)日：2001-11-13
申请号：US09412837
申请日：1999-10-05
IPC分类号： C25D502
CPC分类号： H01L21/32115 , B23H5/08 , H01L21/3212 , H01L21/32134
摘要： A disclosed electroplanarization process involves “masking” certain regions of a wafer surface during electropolishing. The regions chosen for masking are features of relatively low aspect ratio (i.e., features that are wider than they are deep). The masking is accomplished with a material of relatively low ionic conductivity, which effectively slows or blocks transport of the metal ions produced during electropolishing. Examples of masking materials include concentrated phosphoric acid and certain polymers.
摘要翻译： 所公开的电平面化方法涉及在电解抛光期间“掩蔽”晶片表面的某些区域。 选择用于掩蔽的区域是相对低的纵横比的特征（即，比它们更深的特征）。 掩蔽是用离子电导率相对较低的材料完成的，这有效地减慢或阻止了电解抛光过程中产生的金属离子的传输。 掩蔽材料的实例包括浓磷酸和某些聚合物。
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5.发明授权Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation 有权通过选择性搅拌均匀电解抛光镶嵌结构的方法和装置公开(公告)号：US06709565B2
公开(公告)日：2004-03-23
申请号：US09967075
申请日：2001-09-28
IPC分类号： B23H1100
CPC分类号： B23H5/08 , H01L21/32115 , H01L21/3212 , H01L21/32134
摘要： The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
摘要翻译： 本发明涉及在大范围的特征尺寸上具有凹陷和凸起特征的金属表面的平坦化的装置和方法。 本发明通过增加相对于凹陷区域的凸起区域中的流体搅拌来实现。 也就是说，作为金属膜轮廓上的仰角的函数来搅动或更换电抛光浴液的搅动。 海拔越高，浴液的运动或汇率越高。 在本发明的优选方法中，通过使用在电解抛光过程中在晶片表面上移动（接近或接触）的微孔电解抛光垫来实现该搅拌。 因此，本发明的方法是电抛光方法，其在一些情况下包括机械抛光元件。
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公开(公告)号：US5486234A
公开(公告)日：1996-01-23
申请号：US375054
申请日：1995-01-19
IPC分类号： H01L21/3213 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76838 , H01L21/32134
摘要： A process of removing both the field metal, such as copper, and a metal, such as copper, embedded into a dielectric or substrate at substantially the same rate by dripping or spraying a suitable metal etchant onto a spinning wafer to etch the metal evenly on the entire surface of the wafer. By this process the field metal is etched away completely while etching of the metal inside patterned features in the dielectric at the same or a lesser rate. This process is dependent on the type of chemical etchant used, the concentration and the temperature of the solution, and also the rate of spin speed of the wafer during the etching. The process substantially reduces the metal removal time compared to mechanical polishing, for example, and can be carried out using significantly less expensive equipment.
摘要翻译： 通过将合适的金属蚀刻剂滴落或喷涂到旋转的晶片上以均匀地蚀刻金属，以基本上相同的速率将现场金属（例如铜）和金属（例如铜）两者嵌入电介质或基底中的步骤 晶片的整个表面。 通过该处理，在以相同或较小的速率蚀刻电介质中的图案化特征内的金属的同时蚀刻完全场地金属。 该过程取决于所使用的化学蚀刻剂的类型，溶液的浓度和温度，以及蚀刻期间晶片的旋转速度。 例如，与机械抛光相比，该方法显着降低了金属去除时间，并且可以使用显着更便宜的设备进行。
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7.发明授权Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权使用可变电流和质量传递电镀半导体晶片以获得均匀的镀层的方法
公开(公告)号：US06162344A
公开(公告)日：2000-12-19
申请号：US393226
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译： 在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。 作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。 通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。 或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。 这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。 结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。
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公开(公告)号：US06261961B1
公开(公告)日：2001-07-17
申请号：US09258917
申请日：1999-03-01
IPC分类号： H01L21311
CPC分类号： H01L21/32139
摘要： A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO2), silicon nitride (SiNx), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.
摘要翻译： 在核可追溯材料如聚碳酸酯（LEXAN）中形成宽度为100-200nm的核轨道的方法，而不会引起LEXAN的分层。 该方法利用具有惰性氧化物的粘合膜，其允许轨道被充分地扩大到> 200nm，而不会使核可追踪材料分层。 粘合膜可以由诸如二氧化硅（SiO 2），氮化硅（SiN x）和氧化铝（SiO 2）等具有稳定表面的电介质组成的诸如Cr，Ni，Au，Pt或Ti的金属组成， AlO）。 粘附膜可以沉积在栅极金属层的顶部，或者如果粘附膜的性质足够，则可以将其用作栅极层。 通过标准技术如溅射或蒸发来实现粘附膜的沉积。
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9.发明授权Method of electroplating semicoductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权使用可变电流和质量传递电镀半导体晶片的方法以获得均匀的镀层
公开(公告)号：US6110346A
公开(公告)日：2000-08-29
申请号：US393848
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译： 在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。 作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。 通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。 或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。 这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。 结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。
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公开(公告)号：US6033583A
公开(公告)日：2000-03-07
申请号：US851258
申请日：1997-05-05
CPC分类号： C03C17/3417 , C03C15/00 , C03C17/3482 , C03C2218/33
摘要： A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant. The 20-1000 nm diameter holes resulting from the vapor etching process can be useful as molds for electroplating nanometer-sized filaments, etching gate cavities for deposition of nano-cones, developing high-aspect ratio holes in trackable resists, and as filters for a variety of molecular-sized particles in virtually any liquid or gas by selecting the dielectric material that is compatible with the liquid or gas of interest.
摘要翻译： 用于产生高纵横比（即，远大于直径的长度）的电介质材料中的核轨道的蒸汽蚀刻，已经暴露于高能原子粒子的电介质材料中的孤立的圆柱形孔。 该方法包括清洁被跟踪材料的表面并将清洁的表面暴露于合适蚀刻剂的蒸汽。 独立控制蒸汽和跟踪材料的温度提供了单独改变潜在轨道区域和非轨道材料的蚀刻速率的手段。 通常，跟踪区域以比非跟踪区域更大的速率蚀刻。 此外，通过随后在液体蚀刻剂中浸渍，可以使蒸气蚀刻的孔扩大和平滑。 由气相蚀刻工艺产生的20-1000nm直径的孔可用作用于电镀纳米尺寸丝的模具，用于沉积纳米锥体的蚀刻门腔，在可追踪抗蚀剂中显影高纵横比孔，以及用于 通过选择与感兴趣的液体或气体相容的电介质材料，实际上任何液体或气体中的各种分子大小的颗粒。
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