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    FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE
    7.
    发明申请
    FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE 有权
    退出低功率部分宽度高速链接状态时的快速桌面

    公开(公告)号：US20140095751A1

    公开(公告)日：2014-04-03

    申请号：US13631876

    申请日：2012-09-29

    申请人： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Debendra Das Sharma

    发明人： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Debendra Das Sharma

    IPC分类号： G06F13/38

    CPC分类号： G06F13/42 ,  G06F1/3253 ,  G06F13/38 ,  G06F13/382 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

    摘要： Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed.

    摘要翻译： 描述了在退出低功率部分宽度高速链路状态时与快速偏移校正有关的方法和装置。 在一个实施例中，可以在第一时间点上传输有效车道上的出口飞行和/或空闲车道上的唤醒信号/序列，以使链路的一个或多个空闲车道进入活动状态。 在第二时间点（在第一时间点之后或之后），在链路的一个或多个空闲车道上发送训练序列。 并且，一个或多个空闲车道响应于训练序列而在第三时间点之前（在第二时间点之后或之后的其他时间）进行了偏斜校正。 还公开并要求保护其他实施例。

    EMBEDDED CONTROL CHANNEL FOR HIGH SPEED SERIAL INTERCONNECT
    8.
    发明申请
    EMBEDDED CONTROL CHANNEL FOR HIGH SPEED SERIAL INTERCONNECT 有权
    嵌入式控制通道用于高速串行互连

    公开(公告)号：US20140006677A1

    公开(公告)日：2014-01-02

    申请号：US13537837

    申请日：2012-06-29

    申请人： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    发明人： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4291

    摘要： Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.

    摘要翻译： 用于在具有多个数据通道的高速串行互连中嵌入控制信道的方法和装置。 通过使用在周期性地通过一个或多个数据通道发送的控制信道数据来控制互连的操作方面。 使用链路状态周期，其包括链路控制周期，在该链路控制周期期间控制信息通过互连传送，以及链路控制周期之间的链路控制间隔，在链路控制周期期间实现其他链路状态，例如用于传送数据或以低的速率操作链路 电源状态 在发射机和接收机端口处的链路状态周期被同步以考虑链路发射延迟，并且与链路控制信息的双向交换相对应的链路状态周期的定时可以被配置为支持重叠实现或促进请求/响应链路 控制协议。

    Embedded control channel for high speed serial interconnect
    9.
    发明授权
    Embedded control channel for high speed serial interconnect 有权
    用于高速串行互连的嵌入式控制通道

    公开(公告)号：US09229897B2

    公开(公告)日：2016-01-05

    申请号：US13537837

    申请日：2012-06-29

    申请人： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    发明人： Venkatraman Iyer ,  Debendra Das Sharma ,  Robert G. Blankenship ,  Darren S. Jue

    IPC分类号： G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/4291

    摘要： Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.

    摘要翻译： 用于在具有多个数据通道的高速串行互连中嵌入控制信道的方法和装置。 通过使用在周期性地通过一个或多个数据通道发送的控制信道数据来控制互连的操作方面。 使用链路状态周期，其包括链路控制周期，在该链路控制周期期间控制信息通过互连传送，以及链路控制周期之间的链路控制间隔，在链路控制周期期间实现其他链路状态，例如用于传送数据或以低的速率操作链路 电源状态 在发射机和接收机端口处的链路状态周期被同步以考虑链路发射延迟，并且与链路控制信息的双向交换相对应的链路状态周期的定时可以被配置为支持重叠实现或促进请求/响应链路 控制协议。

    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory
    10.
    发明申请
    Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory 有权
    包含/非包含性跟踪本地缓存线以避免缓存行内存上的近内存读取写入两级系统内存

    公开(公告)号：US20150186275A1

    公开(公告)日：2015-07-02

    申请号：US14142045

    申请日：2013-12-27

    申请人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    发明人： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0888

    摘要： A processor is described that includes one or more processing cores. The processing core includes a memory controller to interface with a system memory having a near memory and a far memory. The processing core includes a plurality of caching levels above the memory controller. The processor includes logic circuitry to track state information of a cache line that is cached in one of the caching levels. The state information including a selected one of an inclusive state and a non inclusive state. The inclusive state indicates that a copy or version of the cache line exists in near memory. The non inclusive states indicates that a copy or version of the cache line does not exist in the near memory. The logic circuitry is to cause the memory controller to handle a write request that requests a direct write into the near memory without a read of the near memory beforehand if a system memory write request generated within the processor targets the cache line when the cache line is in the inclusive state.

    摘要翻译： 描述了包括一个或多个处理核心的处理器。 处理核心包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理核心包括存储器控制器上方的多个缓存级别。 处理器包括用于跟踪高速缓存行的状态信息的逻辑电路，该高速缓存行被缓存在缓存级之一中。 所述状态信息包括包含状态和不包含状态中的所选择的状态。 包含状态表示在内存中存在高速缓存行的副本或版本。 不包含状态表示高速缓存行的副本或版本不存在于近端存储器中。 逻辑电路是使存储器控制器处理写入请求，如果在处理器内部产生的系统存储器写入请求在高速缓存线为 在包容性状态。