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公开(公告)号：US20140112339A1
公开(公告)日：2014-04-24
申请号：US14060191
申请日：2013-10-22
申请人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul C. Shah , Sitaraman V. Iyer , Bill Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
发明人： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul C. Shah , Sitaraman V. Iyer , Bill Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC分类号： H04L12/741
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state
摘要翻译： 物理层（PHY）耦合到将包括多个通道的串行差分链路。 PHY包括发射机和接收机，以耦合到车道数量的每个车道。 耦合到每个通道的发射机被配置为将时钟嵌入到要在该通道上发送的数据，并且PHY周期性地发出阻塞链路状态（BLS）请求，以使代理进入BLS以阻止链路层飞行传输， 持续时间 PHY在从包括带内复位，进入低功率状态的进入和进入部分宽度状态的组中选择的PHY相关联任务的持续时间期间利用串行差分链路
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公开(公告)号：US20140115207A1
公开(公告)日：2014-04-24
申请号：US13976937
申请日：2013-03-27
申请人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Debendra Das Sharma , Jeffrey C. Swanson
发明人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Debendra Das Sharma , Jeffrey C. Swanson
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/24 , G06F1/3287 , G06F13/1678 , G06F13/42 , G06F13/4282 , G06N99/005
摘要： A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
摘要翻译： 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。 可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。 在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。
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3.发明申请公开(公告)号：US20140095751A1
公开(公告)日：2014-04-03
申请号：US13631876
申请日：2012-09-29
IPC分类号： G06F13/38
CPC分类号： G06F13/42 , G06F1/3253 , G06F13/38 , G06F13/382 , G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed.
摘要翻译： 描述了在退出低功率部分宽度高速链路状态时与快速偏移校正有关的方法和装置。 在一个实施例中，可以在第一时间点上传输有效车道上的出口飞行和/或空闲车道上的唤醒信号/序列，以使链路的一个或多个空闲车道进入活动状态。 在第二时间点（在第一时间点之后或之后），在链路的一个或多个空闲车道上发送训练序列。 并且，一个或多个空闲车道响应于训练序列而在第三时间点之前（在第二时间点之后或之后的其他时间）进行了偏斜校正。 还公开并要求保护其他实施例。
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公开(公告)号：US20140006677A1
公开(公告)日：2014-01-02
申请号：US13537837
申请日：2012-06-29
IPC分类号： G06F13/40
CPC分类号： G06F13/4291
摘要： Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.
摘要翻译： 用于在具有多个数据通道的高速串行互连中嵌入控制信道的方法和装置。 通过使用在周期性地通过一个或多个数据通道发送的控制信道数据来控制互连的操作方面。 使用链路状态周期，其包括链路控制周期，在该链路控制周期期间控制信息通过互连传送，以及链路控制周期之间的链路控制间隔，在链路控制周期期间实现其他链路状态，例如用于传送数据或以低的速率操作链路 电源状态 在发射机和接收机端口处的链路状态周期被同步以考虑链路发射延迟，并且与链路控制信息的双向交换相对应的链路状态周期的定时可以被配置为支持重叠实现或促进请求/响应链路 控制协议。
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公开(公告)号：US09229897B2
公开(公告)日：2016-01-05
申请号：US13537837
申请日：2012-06-29
CPC分类号： G06F13/4291
摘要： Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.
摘要翻译： 用于在具有多个数据通道的高速串行互连中嵌入控制信道的方法和装置。 通过使用在周期性地通过一个或多个数据通道发送的控制信道数据来控制互连的操作方面。 使用链路状态周期，其包括链路控制周期，在该链路控制周期期间控制信息通过互连传送，以及链路控制周期之间的链路控制间隔，在链路控制周期期间实现其他链路状态，例如用于传送数据或以低的速率操作链路 电源状态 在发射机和接收机端口处的链路状态周期被同步以考虑链路发射延迟，并且与链路控制信息的双向交换相对应的链路状态周期的定时可以被配置为支持重叠实现或促进请求/响应链路 控制协议。
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6.发明申请公开(公告)号：US20140372658A1
公开(公告)日：2014-12-18
申请号：US13994128
申请日：2011-12-07
IPC分类号： G06F13/42
CPC分类号： G06F13/4282 , G06F12/0831 , G06F13/00 , G06F13/14 , G06F13/38 , G06F13/4234 , G06F13/426 , G06F15/781 , G06F2212/621 , G06F2213/0008 , G06F2213/0024 , G06F2213/0026 , H04L12/00
摘要： Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
摘要翻译： 用于通过高速互连传输包括多条交易数据的数据单元的方法，装置和系统。 称为KTI（Keizer Technology Interface）的流量控制单元以支持相干存储器事务的相干多层协议实现。 KTI Flit具有一种基本格式，支持使用可配置字段来实现可用于相应事务的特定格式的KTI Flits。 在一个方面，KTI Flit可以被格式化为用于支持在单个Flit中传送多个相应交易数据的多个时隙。 KTI Flit也可以配置为支持各种类型的事务，并且可以将多个KTI Flits组合成数据包，以支持数据传输，如缓存线传输。
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7.发明授权公开(公告)号：US09442879B2
公开(公告)日：2016-09-13
申请号：US13994128
申请日：2011-12-07
CPC分类号： G06F13/4282 , G06F12/0831 , G06F13/00 , G06F13/14 , G06F13/38 , G06F13/4234 , G06F13/426 , G06F15/781 , G06F2212/621 , G06F2213/0008 , G06F2213/0024 , G06F2213/0026 , H04L12/00
摘要： Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
摘要翻译： 用于通过高速互连传输包括多条交易数据的数据单元的方法，装置和系统。 称为KTI（Keizer Technology Interface）的流量控制单元以支持相干存储器事务的相干多层协议实现。 KTI Flit具有一种基本格式，支持使用可配置字段来实现可用于相应事务的特定格式的KTI Flits。 在一个方面，KTI Flit可以被格式化为用于支持在单个Flit中传送多个相应交易数据的多个时隙。 KTI Flit也可以配置为支持各种类型的事务，并且可以将多个KTI Flits组合成数据包，以支持数据传输，如缓存线传输。
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公开(公告)号：US10671476B2
公开(公告)日：2020-06-02
申请号：US15761405
申请日：2015-09-26
申请人： Intel Corporation , Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
发明人： Daniel S. Froelich , Debendra Das Sharma , Fulvio Spagna , Per E. Fornberg , David Edward Bradley
摘要： There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.
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公开(公告)号：US07571294B2
公开(公告)日：2009-08-04
申请号：US11973209
申请日：2007-10-05
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F12/1441 , G06F12/145
摘要： A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.
摘要翻译： 包含超级页面字段的NoDMA缓存。 超级页面字段指示一组页面何时包含受保护的信息。 计算机系统使用NoDMA缓存来拒绝I / O设备访问系统内存中受保护的信息。
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公开(公告)号：US07296127B2
公开(公告)日：2007-11-13
申请号：US10404881
申请日：2003-03-31
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F12/1441 , G06F12/145
摘要： A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.
摘要翻译： 包含超级页面字段的NoDMA缓存。 超级页面字段指示一组页面何时包含受保护的信息。 计算机系统使用NoDMA缓存来拒绝I / O设备访问系统内存中受保护的信息。
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