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    System and method for memory migration in distributed-memory multi-processor systems
    3.
    发明授权
    System and method for memory migration in distributed-memory multi-processor systems 失效
    分布式存储器多处理器系统中内存迁移的系统和方法

    公开(公告)号：US07103728B2

    公开(公告)日：2006-09-05

    申请号：US10201180

    申请日：2002-07-23

    申请人： Debendra Das Sharma ,  Ashish Gupta ,  William R. Bryg

    发明人： Debendra Das Sharma ,  Ashish Gupta ,  William R. Bryg

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0813 ,  G06F12/0817

    摘要： A distributed-memory multi-processor system includes a plurality of cells communicatively coupled to each other and collectively including a plurality of processors, caches, main memories, and cell controllers. Each of the cells includes at least one of the processors, at least one of the caches, one of the main memories, and one of the cell controllers. Each of the cells is configured to perform memory migration functions for migrating memory from a first one of the main memories to a second one of the main memories in a manner that is invisible to an operating system of the system.

    摘要翻译： 分布式存储器多处理器系统包括通信地彼此耦合并且共同包括多个处理器，高速缓存，主存储器和单元控制器的多个单元。 每个单元包括至少一个处理器，高速缓存，主存储器中的一个和单元控制器之一中的至少一个。 每个单元被配置为执行存储器迁移功能，用于以对系统的操作系统不可见的方式将存储器从主存储器中的第一存储器迁移到主存储器中的第二存储器。

    Virtualization of computer system interconnects
    4.
    发明授权
    Virtualization of computer system interconnects 有权
    虚拟化计算机系统互连

    公开(公告)号：US06832270B2

    公开(公告)日：2004-12-14

    申请号：US10092603

    申请日：2002-03-08

    申请人： Debendra Das Sharma ,  Ashish Gupta

    发明人： Debendra Das Sharma ,  Ashish Gupta

    IPC分类号： G06F300

    CPC分类号： G06F11/2005

    摘要： A virtual input/output (I/O) interconnect mechanism, and a corresponding method, for use in a computer system having a plurality of I/O devices and a plurality of processing units, where I/O devices and processing units are coupled by one or more bridge units, includes an address decode block having a multiplexer that multiplexes inputs to produce an address, where the address relates to a transaction related to a processor unit, a range register decoder that receives the address and provides a destination address of a module to receive the transaction related to the address, and a reroute module identification block that receives the destination address. The reroute module identification block, includes an original module identification that provides an address of one or more original modules in the computer system, and a remapped module identification that provides logical destination module identifications of substitute modules in the computer system, where a substitute module replaces functions of an original module in the computer system.

    摘要翻译： 一种虚拟输入/输出（I / O）互连机制和相应的方法，用于具有多个I / O设备和多个处理单元的计算机系统中，其中I / O设备和处理单元通过 一个或多个桥接单元包括具有多路复用器的地址解码块，该多路复用器复用输入以产生地址，其中地址涉及与处理器单元相关的事务;范围寄存器解码器，其接收地址并提供目的地地址 模块接收与地址相关的交易，以及接收目的地地址的重新路由模块识别块。 重新路由模块识别块包括提供计算机系统中的一个或多个原始模块的地址的原始模块标识，以及在计算机系统中提供替代模块的逻辑目的地模块标识的重新映射的模块标识，其中替代模块替换 计算机系统中原始模块的功能。

    System and method for input/output module virtualization and memory interleaving using cell map
    5.
    发明授权
    System and method for input/output module virtualization and memory interleaving using cell map 失效
    使用单元格映射的输入/输出模块虚拟化和内存交错的系统和方法

    公开(公告)号：US06807603B2

    公开(公告)日：2004-10-19

    申请号：US10080739

    申请日：2002-02-22

    申请人： Ashish Gupta ,  Debendra Das Sharma

    发明人： Ashish Gupta ,  Debendra Das Sharma

    IPC分类号： G06F1208

    CPC分类号： G06F12/0607

    摘要： A method of accessing a plurality of memories and a plurality of input/output modules includes providing at least one map table, including a plurality of entries. Each entry includes an entry type identifier and a plurality of entry items. A first logical address including a plurality of address bits is received. An entry in the at least one map table is identified based on a first set of the address bits. A type of the identified entry is determined based on the entry type identifier of the identified entry. An entry item in the identified entry is identified based on a second set of the address bits if the entry type identifier indicates an input/output type entry. An entry item in the identified entry is identified based on a third set of the address bits if the entry type identifier indicates a memory type entry.

    摘要翻译： 一种访问多个存储器和多个输入/输出模块的方法包括提供包括多个条目的至少一个映射表。 每个条目包括条目类型标识符和多个条目项。 接收包括多个地址位的第一逻辑地址。 基于第一组地址位来识别至少一个映射表中的条目。 所识别的条目的类型基于所识别的条目的条目类型标识来确定。 如果条目类型标识符指示输入/输出类型条目，则基于第二组地址位来识别所标识条目中的条目项。 如果条目类型标识符指示存储器类型条目，则基于第三组地址位来识别所标识条目中的条目项。

    Verification of asynchronous boundary behavior
    6.
    发明授权
    Verification of asynchronous boundary behavior 失效
    验证异步边界行为

    公开(公告)号：US06598191B1

    公开(公告)日：2003-07-22

    申请号：US09444610

    申请日：1999-11-23

    申请人： Debendra Das Sharma ,  Ashish Gupta ,  Donald A. Williamson

    发明人： Debendra Das Sharma ,  Ashish Gupta ,  Donald A. Williamson

    IPC分类号： G01R313177

    CPC分类号： G01R31/318525

    摘要： A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system. By inserting the delay register/multiplexer at or after the asynchronous boundary, any signal level uncertainty present between the read domain and the write domain is captured and propagated through the digital system.

    摘要翻译： 用于验证数字系统的异步边界行为的功能。 异步边界形成在由写时钟（写域）计时的第一串寄存器和由读时钟（读域）计时的第二寄存器组之间的耦合上。 在数字系统中的预定寄存器之后插入延迟寄存器和多路复用器，其中预定寄存器和延迟寄存器由相同的时钟计时。 预定寄存器的输出耦合到多路复用器的第一输入端和延迟寄存器的第一输入端。 延迟寄存器耦合到多路复用器的第二输入端。 选择器耦合到多路复用器，用于选择两个多路复用器输入中的哪一个传递到数字系统中的后续寄存器。 通过在异步边界之后或之后插入延迟寄存器/多路复用器，读取域和写入域之间存在的任何信号电平不确定度被捕获并通过数字系统传播。

    Pass through debug port on a high speed asynchronous link
    7.
    发明授权
    Pass through debug port on a high speed asynchronous link 有权
    通过高速异步链路上的调试端口

    公开(公告)号：US07328375B2

    公开(公告)日：2008-02-05

    申请号：US10749660

    申请日：2003-12-30

    申请人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    发明人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    IPC分类号： G06F11/00

    CPC分类号： H04L7/046

    摘要： An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

    摘要翻译： 示例性计算机系统包括包括接口控制器的第一桥接设备。 接口控制器将桥接设备内生成的调试信息与训练模式相结合。 第一桥接器件经由高速异步互连耦合到第二桥接器件。 第一桥接器件将调试信息和训练模式转换成要通过互连发送到第二桥接器件的分组。 训练模式用于允许第二桥接设备在传送期间维持比特和符号同步; 的调试信息。

    Pass through debug port on a high speed asynchronous link
    8.
    发明申请
    Pass through debug port on a high speed asynchronous link 有权
    通过高速异步链路上的调试端口

    公开(公告)号：US20050149705A1

    公开(公告)日：2005-07-07

    申请号：US10749660

    申请日：2003-12-30

    申请人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    发明人： Ashish Gupta ,  Bahaa Fahim ,  Kent Dickey ,  Jonathan Jasper

    IPC分类号： G06F7/38 ,  G06F13/00 ,  H04L7/04

    CPC分类号： H04L7/046

    摘要： An example computer system includes a first bridge device that includes an interface controller. The interface controller combines debug information generated within the bridge device with a training pattern. The first bridge device is coupled to a second bridge device via a high-speed asynchronous interconnect. The first bridge device converts the debug information and training pattern into a packet to be transmitted over the interconnect to the second bridge device. The training pattern serves to allow the second bridge device to maintain bit and symbol synchronization during the transfer; of the debug information.

    摘要翻译： 示例性计算机系统包括包括接口控制器的第一桥接设备。 接口控制器将桥接设备内生成的调试信息与训练模式相结合。 第一桥接器件经由高速异步互连耦合到第二桥接器件。 第一桥接器件将调试信息和训练模式转换成要通过互连发送到第二桥接器件的分组。 训练模式用于允许第二桥接设备在传送期间维持比特和符号同步; 的调试信息。

    Programmable delay elements for source synchronous link function design verification through simulation
    9.
    发明授权
    Programmable delay elements for source synchronous link function design verification through simulation 有权
    用于源同步链路功能设计验证的可编程延迟元件

    公开(公告)号：US06611936B2

    公开(公告)日：2003-08-26

    申请号：US09560191

    申请日：2000-04-28

    申请人： Darren S. Jue ,  Ashish Gupta

    发明人： Darren S. Jue ,  Ashish Gupta

    IPC分类号： G01R3128

    CPC分类号： G06F17/5022

    摘要： A method and apparatus are disclosed for verifying the functional design of a system's response to propagation delays from the inputs of source synchronous links during testing. The system emulates propagation delays by receiving data slice from a source, applying a random or known delay to the data slice, and sending the delayed data slice to the chip under test. In one embodiment, multiple data slices having varying delay values may be used to test combinations of delays. A programmable delay.element is used to emulate the propagation delays. This is may be implemented at the hardware description level by receiving the data slice onto multiple data buses, applying a different delay to the data slice on each data bus, and sending the delayed data slices as inputs into a multiplexor. The multiplexor may have a selector input that determines which amount of delay to test. Alternatively, the delay may be emulated using a higher level programming language and creating a multidimensional array. In one dimension, the array receives different data slices, and in the other it assigns different delay values. The multidimensional array then receives multiple data slices at the same time. Each delay value is stored in a different array location, depending upon the delay assigned to the data slice. An output entry is sent to the chip under test. The array entries may be shifted each clock cycle to the output entry, or a pointer may be used to specify a different output entry each clock cycle.

    摘要翻译： 公开了一种用于验证系统在测试期间来自源同步链路的输入对传播延迟的响应的功能设计的方法和装置。 该系统通过从源接收数据切片来对传播延迟进行仿真，将随机或已知的延迟应用于数据切片，并将延迟的数据切片发送到被测芯片。 在一个实施例中，可以使用具有变化的延迟值的多个数据切片来测试延迟的组合。 可编程的delay.element用于模拟传播延迟。 这可以通过在多个数据总线上接收数据切片，对每个数据总线上的数据切片应用不同的延迟，并将延迟的数据切片作为输入发送到多路复用器中，在硬件描述级别上实现。 多路复用器可以具有选择器输入，确定要测试的延迟量。 或者，可以使用更高级别的编程语言来模拟延迟并创建多维数组。 在一个维度上，阵列接收不同的数据切片，另一方面分配不同的延迟值。 然后，多维数组同时接收多个数据片段。 每个延迟值存储在不同的阵列位置，这取决于分配给数据切片的延迟。 输出条目发送到被测芯片。 阵列条目可以每个时钟周期移动到输出条目，或者可以使用指针来指定每个时钟周期的不同输出条目。