公开(公告)号：US09236342B2

公开(公告)日：2016-01-12

申请号：US14133385

申请日：2013-12-18

申请人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

发明人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

IPC分类号： H01L21/311 ,  H01L23/522 ,  H01L21/768 ,  H01L21/027 ,  H01L23/532

CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

摘要翻译： 描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。 在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中 第二光栅的线。 介电材料的区域由交联的可光致发光材料组成。

公开(公告)号：US20150171010A1

公开(公告)日：2015-06-18

申请号：US14133385

申请日：2013-12-18

申请人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

发明人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

IPC分类号： H01L23/522 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

摘要翻译： 描述了用于后端（BEOL）互连的带有光触点的自对准通孔和插头图案。 在一个示例中，用于集成电路的互连结构包括设置在衬底上方的互连结构的第一层，第一层具有在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 集成电路还包括布置在互连结构的第一层之上的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 集成电路还包括设置在第一光栅的金属线和第二光栅的金属线之间的电介质材料区域，并且在与第一光栅的介质线的上部和电介质的下部相同的平面中 第二光栅的线。 介电材料的区域由交联的可光致发光材料组成。

公开(公告)号：US20160104642A1

公开(公告)日：2016-04-14

申请号：US14965734

申请日：2015-12-10

申请人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

发明人： Robert L. Bristol ,  Kevin Lin ,  Kanwal Jit Singh ,  Alan M. Myers ,  Richard E. Schenker

IPC分类号： H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

公开(公告)号：US20150214094A1

公开(公告)日：2015-07-30

申请号：US14163323

申请日：2014-01-24

申请人： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

发明人： Christopher J. Jezewski ,  Jasmeet S. Chawla ,  Kanwal Jit Singh ,  Alan M. Myers ,  Elliot N. Tan ,  Richard E. Schenker

IPC分类号： H01L21/768

CPC分类号： H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to formed interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminated the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allows for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

摘要翻译： 用于形成在电介质层内具有紧密间距互连结构的互连层的工艺，其中用于形成的互连结构的沟槽和通孔在金属化之前具有相对低的纵横比。 当沉积时，低纵横比可以减少或基本上消除在金属化材料内形成的空隙的电位。 本文的实施例可以通过允许在金属化之前去除用于形成沟槽和通孔的结构的工艺来实现这种相对低的纵横比。

公开(公告)号：US09406512B2

公开(公告)日：2016-08-02

申请号：US14720821

申请日：2015-05-24

申请人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

发明人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.

公开(公告)号：US20150255284A1

公开(公告)日：2015-09-10

申请号：US14720821

申请日：2015-05-24

申请人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

发明人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

IPC分类号： H01L21/033 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.

摘要翻译： 描述了通过用于后端（BEOL）互连的多色photobuckets图案化的自对准。 在一个示例中，用于集成电路的互连结构包括布置在衬底上方的互连结构的第一层，第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 所述互连结构的第二层设置在所述互连结构的所述第一层上方，所述第二层包括垂直于所述第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一和第二电介质区域设置在第一光栅的金属线和第二光栅的金属线之间，并且在与第一光栅的介电线的上部和第二栅的介电线的下部相同的平面中 光栅。 第一电介质区域由第一交联光可光化材料组成，第二电介质区域由第二不同的交联光可光化材料组成。

公开(公告)号：US09041217B1

公开(公告)日：2015-05-26

申请号：US14133344

申请日：2013-12-18

申请人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

发明人： Robert L. Bristol ,  James M. Blackwell ,  Alan M. Myers ,  Kanwal Jit Singh

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. A second layer of the interconnect structure is disposed above the first layer of the interconnect structure, the second layer including a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. First and second dielectric regions are disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The first dielectric region is composed of a first cross-linked photolyzable material, and the second dielectric region is composed of a second, different, cross-linked photolyzable material.

摘要翻译： 描述了通过用于后端（BEOL）互连的多色photobuckets图案化的自对准。 在一个示例中，用于集成电路的互连结构包括布置在衬底上方的互连结构的第一层，第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 所述互连结构的第二层设置在所述互连结构的所述第一层上方，所述第二层包括垂直于所述第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有比第二光栅的金属线的最下表面低的最低表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一和第二电介质区域设置在第一光栅的金属线和第二光栅的金属线之间，并且在与第一光栅的介电线的上部和第二栅的介电线的下部相同的平面中 光栅。 第一电介质区域由第一交联光可光化材料组成，第二电介质区域由第二不同的交联光可光化材料组成。

公开(公告)号：US20160126184A1

公开(公告)日：2016-05-05

申请号：US14931175

申请日：2015-11-03

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

公开(公告)号：US09209077B2

公开(公告)日：2015-12-08

申请号：US14137588

申请日：2013-12-20

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

摘要翻译： 描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅，并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。 蚀刻涉及去除一个或多个牺牲材料的一部分。

公开(公告)号：US09548269B2

公开(公告)日：2017-01-17

申请号：US14931175

申请日：2015-11-03

申请人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

发明人： Alan M. Myers ,  Kanwal Jit Singh ,  Robert L. Bristol ,  Jasmeet S. Chawla

IPC分类号： H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L21/311

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

摘要翻译： 描述了使用对角线硬掩模进行自对准通孔和插头图案，以改进制造后端（BEOL）互连的覆盖。 在一个示例中，制造用于集成电路的互连结构的方法包括在布置在衬底上方的层间介电层上形成第一硬掩模层。 第一硬掩模层包括多个第一硬掩模线，其具有在第一方向上的第一光栅并且包括与第一光栅交错的一个或多个牺牲材料。 该方法还涉及在第一硬掩模层之上形成第二硬掩模层。 第二硬掩模层包括多个第二硬掩模线，所述第二硬掩模线在第二方向上具有与第一方向对角的第二光栅。 该方法还涉及使用第二硬掩模层作为掩模，蚀刻第一硬掩模层以形成图案化的第一硬掩模层。 蚀刻涉及去除一个或多个牺牲材料的一部分。