公开(公告)号：US20070020930A1

公开(公告)日：2007-01-25

申请号：US11526116

申请日：2006-09-22

申请人： Robert Lander ,  Marcus van Dal ,  Jacob Hooker

发明人： Robert Lander ,  Marcus van Dal ,  Jacob Hooker

IPC分类号： H01L21/44

CPC分类号： H01L21/28079 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

摘要： A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.

摘要翻译： 公开了一种半导体器件，其通过方法制造，具有半导体结构，其具有在衬底的表面中和/或表面上形成至少一个连接区域的硅区域。 在一个实施例中，该方法包括：i）至少在硅区域形成来自第一金属的金属簇层，使得在金属簇​​层中，金属簇与不存在金属簇的位置交替，第一 金属在预定条件下是非硅化金属，ii）在金属簇层的顶部上沉积第二金属的金属层，第二金属是硅化金属，和iii）在预定条件下进行至少一次热处理 在第二金属层上，以便通过第二金属与硅区域的反应形成金属硅化物，其中第一金属的原子在基本上垂直于衬底表面的方向上移位。

公开(公告)号：US20050112875A1

公开(公告)日：2005-05-26

申请号：US10966141

申请日：2004-10-15

申请人： Robert Lander ,  Marcus van Dal ,  Jacob Hooker

发明人： Robert Lander ,  Marcus van Dal ,  Jacob Hooker

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/20 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28079 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

摘要： One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.

摘要翻译： 本发明的一个实施例涉及一种用于制造具有半导体结构的半导体器件的方法，所述半导体器件具有在衬底的表面中和/或表面上形成至少一个连接区域的硅区域。 该方法包括由第一非硅化金属形成金属簇层，随后沉积由第二硅化金属构成的金属层。 随后的热处理负责从第二金属形成金属硅化物，第一金属的原子在基本上垂直于衬底的表面的方向上移位。 根据本发明的一个实施方案，第一金属的原子由Kirkendall效应位移到金属硅化物的下方。 例如，如果制造MOST，则在源极和漏极区域以及栅电极的位置都具有优点。

公开(公告)号：US20090302389A1

公开(公告)日：2009-12-10

申请号：US12066707

申请日：2006-09-11

申请人： Robert Lander ,  Mark Van Dal ,  Jacob Hooker

发明人： Robert Lander ,  Mark Van Dal ,  Jacob Hooker

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28097 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/78

摘要： A method is described for forming gate structures with different metals on a single substrate. A thin semiconductor layer (26) is formed over gate dielectric (24) and patterned to be present in a first region (16) not a second region (18). Then, metal (30) is deposited and patterned to be present in the second region not the first. Then, a fully suicided gate process is carried out to result in a fully suicided gate structure in the first region and a gate structure in the second region including the fully suicided gate structure above the deposited metal (30).

摘要翻译： 描述了在单个衬底上形成具有不同金属的栅极结构的方法。 在栅极电介质（24）上形成薄的半导体层（26），并被图案化以存在于不是第二区域（18）的第一区域（16）中。 然后，金属（30）被沉积并图案化以存在于不是第一区域的第二区域中。 然后，进行完全自动的栅极处理，以在第一区域中产生完全自述的栅极结构，并且在第二区域中的栅极结构包括沉积金属（30）上方的完全自蚀的栅极结构。

公开(公告)号：US20060134848A1

公开(公告)日：2006-06-22

申请号：US10544413

申请日：2004-01-15

申请人： Robert Lander ,  Jacob Hooker ,  Robertus Wolters

发明人： Robert Lander ,  Jacob Hooker ,  Robertus Wolters

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/321 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L29/4958 ,  H01L29/4966

摘要： Method of manufacturing a semiconductor device comprising MOS transistors having gate electrodes (15, 16) formed in a number of metal layers (8, 9, 13; 8, 12, 13) deposited upon one another. In this method, active silicon regions (4, 5) provided with a layer of a gate dielectric (7) and field-isolation regions (6) insulating these regions with respect to each other are formed in a silicon body (1). Then, a layer off a first metal (8) is deposited in which locally, at the location of a part of the active regions (4), nitrogen is introduced. On the layer of the first metal, a layer of a second metal (13) is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal (9) which is permeable to nitrogen is deposited on the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric. Substantial changes of the metal work function are possible, and a semiconductor device comprising NMOS and PMOS can be realized.

摘要翻译： 一种制造半导体器件的方法，包括：MOS晶体管，其具有形成在彼此沉积的多个金属层（8,9,13; 8,12,13）中的栅电极（15,16）。 在这种方法中，在硅体（1）中形成具有栅极电介质层（7）的层和在这些区域彼此绝缘的场隔离区域（6）的有源硅区域（4,5）。 然后，沉积第一金属（8）上的层，其中局部地在一部分有源区（4）的位置处引入氮。 在第一金属层上沉积第二金属层（13），然后在金属层中蚀刻栅电极。 在将氮气引入第一金属层之前，在第一金属层上沉积有氮渗透的第三金属（9）的辅助层。 因此，第一金属层可以局部氮化，而不会损坏下面的栅极电介质。 可以实现金属功函数的显着变化，并且可以实现包括NMOS和PMOS的半导体器件。

公开(公告)号：US08994112B2

公开(公告)日：2015-03-31

申请号：US13063504

申请日：2009-09-10

申请人： Gerben Doornbos ,  Robert Lander

发明人： Gerben Doornbos ,  Robert Lander

IPC分类号： H01L21/70 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

摘要： A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si3N4) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k≧5, k≧7.5, and k≧20.

摘要翻译： 翅片（12）具有掺杂有第一导电类型的上部（30）和掺杂有第二导电类型的下部（32）的翅片（FET），其中，所述上部（30）和 下部（32）用作二极管; 并且所述FinFET还包括：与所述鳍片（12）的至少一侧相邻的高k电介质材料（例如Si 3 N 4）的至少一个层（26,28），用于在所述二极管上更均匀地重新分配电位降，与 如果不存在至少一层高k电介质材料，当上部（30）连接到第一电位并且下部（32）连接到第二电位时，从而提供跨越结的电位降 （34）。 高k电介质材料的k值的例子为k≥5，k≥7.5，k≥20。

公开(公告)号：US20110169101A1

公开(公告)日：2011-07-14

申请号：US13063504

申请日：2009-09-10

申请人： Gerben Doornbos ,  Robert Lander

发明人： Gerben Doornbos ,  Robert Lander

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7856 ,  H01L21/76224 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

摘要： A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si3N4) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k≧5, k≧7.5, and k≧20.

摘要翻译： 翅片（12）具有掺杂有第一导电类型的上部（30）和掺杂有第二导电类型的下部（32）的翅片（FET），其中，所述上部（30）和 下部（32）用作二极管; 并且所述FinFET还包括：与所述鳍片（12）的至少一侧相邻的高k电介质材料（例如Si 3 N 4）的至少一个层（26,28），用于在所述二极管上更均匀地重新分配电位降，与 如果不存在至少一层高k电介质材料，当上部（30）连接到第一电位并且下部（32）连接到第二电位时，从而提供跨越结的电位降 （34）。 高k电介质材料的k值的例子为k≥5，k≥7.5，k≥20。

公开(公告)号：US07326631B2

公开(公告)日：2008-02-05

申请号：US10544413

申请日：2004-01-15

申请人： Robert Lander ,  Jacob Christopher Hooker ,  Robertus Adrianus Maria Wolters

发明人： Robert Lander ,  Jacob Christopher Hooker ,  Robertus Adrianus Maria Wolters

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L21/321 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L29/4958 ,  H01L29/4966

摘要： Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.

摘要翻译： 与示例实施例一致，制造半导体器件的方法包括MOS晶体管，其栅极形成在彼此沉积的多个金属层中。 在硅体中形成具有将这些区域彼此绝缘的栅极电介质层和场隔离区域的有源硅区域。 然后，沉积一层第一金属，其中局部地，在一部分活性区域中引入氮。 在第一金属层上沉积第二金属层，然后在金属层中蚀刻栅电极。 在将氮气引入到第一金属层中之前，将可渗氮的第三金属的辅助层沉积在第一金属层上。 因此，第一金属层可以局部氮化，而不会损坏下面的栅极电介质。

公开(公告)号：US07763944B2

公开(公告)日：2010-07-27

申请号：US11574245

申请日：2005-08-10

申请人： Jacob C. Hooker ,  Robert Lander ,  Robertus Wolters

发明人： Jacob C. Hooker ,  Robert Lander ,  Robertus Wolters

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： The invention relates to a CMOS device (10) with an NMOST I and PMOST 2 having gate regions (1D,2D) comprising a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and both comprise as the further element an element selected from the group comprising carbon, oxygen and the chalcogenides. Preferably both the first and second conducting material comprise a compound of molybdenum and carbon or oxygen. The invention also provides an attractive method of manufacturing such a device.

摘要翻译： 本发明涉及具有NMOST I和PMOST 2的CMOS器件（10），栅极区（1D，2D）包括含有金属和另一元素的化合物。 根据本发明，第一和第二导电材料都包含含有选自钼和钨的金属作为金属的化合物，并且都包含选自碳，氧和硫族化物的元素作为另外的元素。 优选地，第一和第二导电材料都包含钼和碳或氧的化合物。 本发明还提供了制造这种装置的有吸引力的方法。

公开(公告)号：US20080211032A1

公开(公告)日：2008-09-04

申请号：US11574245

申请日：2005-08-10

申请人： Jacob C. Hooker ,  Robert Lander ,  Robertus Wolters

发明人： Jacob C. Hooker ,  Robert Lander ,  Robertus Wolters

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： The invention relates to a CMOS device (10) with an NMOST I and PMOST 2 having gate regions (1D,2D) comprising a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and both comprise as the further element an element selected from the group comprising carbon, oxygen and the chalcogenides. Preferably both the first and second conducting material comprise a compound of molybdenum and carbon or oxygen. The invention also provides an attractive method of manufacturing such a device.

摘要翻译： 本发明涉及具有NMOST I和PMOST 2的CMOS器件（10），其具有栅极区域（1D，2D），其包含含有金属和另一元素的化合物。 根据本发明，第一和第二导电材料都包含含有选自钼和钨的金属作为金属的化合物，并且都包含选自碳，氧和硫族化物的元素作为另外的元素。 优选地，第一和第二导电材料都包含钼和碳或氧的化合物。 本发明还提供了制造这种装置的有吸引力的方法。

公开(公告)号：US07320939B2

公开(公告)日：2008-01-22

申请号：US11526116

申请日：2006-09-22

申请人： Robert Lander ,  Marcus Johannes Henricus van Dal ,  Jacob Christopher Hooker

发明人： Robert Lander ,  Marcus Johannes Henricus van Dal ,  Jacob Christopher Hooker

IPC分类号： H01L21/44

CPC分类号： H01L21/28079 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665

摘要： A semiconductor device, fabricated by a method, having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate is disclosed. In one embodiment, the method includes i) forming, at least at the silicon region, a metal cluster layer from a first metal, such that, in the metal cluster layer, metal clusters alternate with sites where there are no metal clusters, the first metal being a non-siliciding metal at predetermined conditions, ii) depositing a metal layer of a second metal on top of the metal cluster layer, the second metal being a siliciding metal and iii) carrying out at least one heat treatment at the predetermined conditions on the second metal layer so as to form metal silicide through reaction of the second metal with the silicon region, wherein atoms of the first metal are displaced in a direction substantially perpendicular to the surface of the substrate.

摘要翻译： 公开了一种半导体器件，其通过方法制造，具有半导体结构，其具有在衬底的表面中和/或表面上形成至少一个连接区域的硅区域。 在一个实施例中，该方法包括：i）至少在硅区域形成来自第一金属的金属簇层，使得在金属簇​​层中，金属簇与不存在金属簇的位置交替，第一 金属在预定条件下是非硅化金属，ii）在金属簇层的顶部上沉积第二金属的金属层，第二金属是硅化金属，和iii）在预定条件下进行至少一次热处理 在第二金属层上，以便通过第二金属与硅区域的反应形成金属硅化物，其中第一金属的原子在基本上垂直于衬底表面的方向上移位。