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    Digital data synchronizer
    1.
    发明授权
    Digital data synchronizer 失效
    数字数据同步器

    公开(公告)号：US5163070A

    公开(公告)日：1992-11-10

    申请号：US623825

    申请日：1990-12-07

    申请人： Robert R. N. Bielby ,  Richard L. Couchman ,  Leo T. Van Lahr

    发明人： Robert R. N. Bielby ,  Richard L. Couchman ,  Leo T. Van Lahr

    IPC分类号： H04L7/04

    CPC分类号： H04L7/042 ,  G11B20/1833 ,  H04L7/043

    摘要： A digital data synchronizer, synchronizes a digital data system to an incoming serial bit stream having a segment of pseudo random bit sequence, which is a function of a predetermined primitive polynomial, preceeding the start of data. The synchronizer includes a first feedback shift register configured as a multiplier for generating the pseudo random bit sequence. The multiplier register operates on the incoming serial bit stream to determine whether a valid bit sequence of the primitive polynomial is present in the incoming serial bit stream, and if it is, a zero output is produced. A second feedback shift register configured as a divider produces a pseudo random bit sequence which is also a function of the predetermined primitive polynomial. A counter is provided to monitor the number of zeros outputted by the multiplier feedback shift register. When a preset count is reached, the contents of the multiplier shift register is parallel loaded into the divider shift register if the bit sequence of the divider shift register does not match the bit sequence of the incoming serial data. Thus, the divider pseudo random sequence is synchronized to the incoming serial data. A synch word detector monitors the parallel contents of the divider register. When the synch word detector detects a predetermined word in the pseudo random bit sequence produced by the divider, it produces an output flag which indicates the next bit in the incoming digital data word is the first data bit.

    摘要翻译： 数字数据同步器将数字数据系统与具有在数据开始之前的预定原始多项式的函数的具有伪随机位序列的段的输入串行比特流同步。 同步器包括配置为用于产生伪随机位序列的乘法器的第一反馈移位寄存器。 乘数寄存器对输入的串行比特流进行操作，以确定输入串行比特流中是否存在原始多项式的有效比特序列，如果是，则产生零输出。 配置为分频器的第二反馈移位寄存器产生伪随机比特序列，该伪随机比特序列也是预定原始多项式的函数。 提供一个计数器来监视乘法器反馈移位寄存器输出的零数。 当达到预设计数时，如果分频器移位寄存器的位序列与输入串行数据的位序列不匹配，则乘法器移位寄存器的内容将并行加载到分频器移位寄存器中。 因此，分频器伪随机序列与输入的串行数据同步。 同步字检测器监视分频器寄存器的并行内容。 当同步字检测器检测到由分频器产生的伪随机位序列中的预定字时，其产生输出标志，其指示输入数字数据字中的下一位是第一数据位。

    Phase-locked loop or delay-locked loop circuitry for programmable logic devices
    2.
    发明授权
    Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环或延迟锁定环电路

    公开(公告)号：US06437650B1

    公开(公告)日：2002-08-20

    申请号：US09855865

    申请日：2001-05-15

    申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

    发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

    IPC分类号： H03L706

    CPC分类号： G06F1/10 ,  H03L7/0812 ,  H03L7/0996 ,  H03L7/0997

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分 主PLL / DLL输出信号。 以这种方式，分布式反馈环路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号经历的分布延迟的基本精确的匹配。

    Reducing I/O noise when leaving programming mode
    3.
    发明授权
    Reducing I/O noise when leaving programming mode 有权
    离开编程模式时减少I / O噪声

    公开(公告)号：US06242941B1

    公开(公告)日：2001-06-05

    申请号：US09320858

    申请日：1999-05-26

    申请人： W. Bradley Vest ,  Mark W. Fiester ,  Myron W. Wong ,  John C. Costello ,  Robert R. N. Bielby ,  Krishna Rangasayee

    发明人： W. Bradley Vest ,  Mark W. Fiester ,  Myron W. Wong ,  John C. Costello ,  Robert R. N. Bielby ,  Krishna Rangasayee

    IPC分类号： H03K1716

    CPC分类号： H03K19/00346

    摘要： An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (125) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (210) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.

    摘要翻译： 集成电路包含以这种方式操作以在将输出电路从编程模式切换到用户模式时降低输出噪声的电路。 在实现中，集成电路（125）可以在具有用户配置数据的编程模式下配置。 在用户模式下，集成电路将以编程模式下用户定义的功能运行。 当从编程模式切换到用户模式时，集成电路的每个输出（210）将切换到其用户模式值。 为了最小化开关噪声，输出不会全部被释放到用户模式值。

    Phase-locked loop circuitry for programmable logic devices
    6.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06469553B1

    公开(公告)日：2002-10-22

    申请号：US09811946

    申请日：2001-03-19

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L700

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。

    Phase-locked loop circuitry for programmable logic devices
    7.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06218876B1

    公开(公告)日：2001-04-17

    申请号：US09392095

    申请日：1999-09-08

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L706

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。

    Programming circuits and techniques for programming logic
    8.
    发明授权
    Programming circuits and techniques for programming logic 失效
    用于编程逻辑的编程电路和技术

    公开(公告)号：US5590305A

    公开(公告)日：1996-12-31

    申请号：US572806

    申请日：1995-12-15

    申请人： Richard S. Terrill ,  Robert R. N. Bielby

    发明人： Richard S. Terrill ,  Robert R. N. Bielby

    IPC分类号： G06F11/14 ,  G06F15/177 ,  G06F13/00

    CPC分类号： G06F11/1417 ,  G06F15/177

    摘要： Apparatus and methods for configuring a plurality of programmable logic devices which include the steps of providing a source of configuration data and transferring the configuration data directly from the source to each of the programmable logic devices. In some embodiments, the methods permit the programmable logic devices to configure themselves without the intervention of an intelligent host such as a CPU, a microcontroller, or other types of intelligent logic. In other embodiments, configuration data files are used in conjunction with an intelligent host to configure the programmable logic devices. Configuration is performed at power-up or, alternatively, under user or software control.

    摘要翻译： 用于配置多个可编程逻辑器件的装置和方法包括以下步骤：提供配置数据源，并将配置数据直接从源传送到每个可编程逻辑器件。 在一些实施例中，该方法允许可编程逻辑器件配置自身而不需要诸如CPU，微控制器或其他类型的智能逻辑的智能主机的介入。 在其他实施例中，配置数据文件与智能主机结合使用以配置可编程逻辑设备。 配置在上电时或在用户或软件控制下执行。

    Phase-locked loop or delay-locked loop circuitry for programmable logic devices
    10.
    发明授权
    Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环或延迟锁定环电路

    公开(公告)号：US06177844B1

    公开(公告)日：2001-01-23

    申请号：US09393036

    申请日：1999-09-09

    申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

    发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Robert R. N. Bielby

    IPC分类号： H03L706

    CPC分类号： G06F1/10 ,  H03L7/0812 ,  H03L7/0996 ,  H03L7/0997

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分 主PLL / DLL输出信号。 以这种方式，分布式反馈回路电路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号所经历的分布延迟的基本精确匹配。