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    Phase-locked loop circuitry for programmable logic devices
    1.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06469553B1

    公开(公告)日：2002-10-22

    申请号：US09811946

    申请日：2001-03-19

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L700

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。

    Phase-locked loop circuitry for programmable logic devices
    2.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06218876B1

    公开(公告)日：2001-04-17

    申请号：US09392095

    申请日：1999-09-08

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L706

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。

    Techniques for programming programmable logic array devices
    3.
    发明授权
    Techniques for programming programmable logic array devices 失效
    用于编程可编程逻辑阵列器件的技术

    公开(公告)号：US5543730A

    公开(公告)日：1996-08-06

    申请号：US442801

    申请日：1995-05-17

    申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard S. Terrill ,  Rina Raman ,  Robert R. N. Bielby

    发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard S. Terrill ,  Rina Raman ,  Robert R. N. Bielby

    IPC分类号： G06F17/50 ,  H03K19/177

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

    摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

    摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

    High-speed programmable interconnect
    7.
    发明授权
    High-speed programmable interconnect 有权
    高速可编程互连

    公开(公告)号：US06384629B2

    公开(公告)日：2002-05-07

    申请号：US09738403

    申请日：2000-12-15

    申请人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    发明人： Joseph Huang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  Xiaobao Wang ,  Richard G. Cliff

    IPC分类号： H01L2500

    CPC分类号： H03K19/17736 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17792

    摘要： An improved interconnection between horizontal conductors and the input to logic elements. A signal regeneration circuit is provided in the path between the horizontal conductor and the logic element, thereby isolating and boosting the signal. This allows for faster switching operation. A path is provided allowing the selective routing of signals from the horizontal conductors to the vertical conductors, without passing through a logic element. Also, a path is provided to allow a horizontal conductors to be routed to any of a plurality of vertical conductors.

    摘要翻译： 水平导体与逻辑元件输入之间的互连改善。 在水平导体和逻辑元件之间的路径中提供信号再生电路，从而隔离和升高信号。 这允许更快的切换操作。 提供路径，允许从水平导体到垂直导体的信号的选择性路由，而不通过逻辑元件。 而且，提供了一种路径，以允许水平导体被路由到多个垂直导体中的任何一个。

    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device
    8.
    发明授权
    LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device 有权
    LVDS接口结合了可编程逻辑器件中的锁相环电路

    公开(公告)号：US06373278B1

    公开(公告)日：2002-04-16

    申请号：US09758674

    申请日：2001-01-11

    申请人： Chiakang Sung ,  Bonnie I. Wang ,  Richard G. Cliff

    发明人： Chiakang Sung ,  Bonnie I. Wang ,  Richard G. Cliff

    IPC分类号： H03K19173

    CPC分类号： H03L7/18 ,  H03L7/07 ,  H03L7/0891

    摘要： An LVDS interface for a programmable logic device uses phase-locked loop (“PLL”) circuits to provide data clocks for data input and output. The PLL clocks are highly accurate and each includes a multiply-by-W counter so that a multiplied and an unmultiplied clock are available. The multiplied clock is used to clock data into or out of a shift register chain serially. The unmultiplied clock is used to load or read the registers in the shift register chain in parallel. Providing both the multiplied and unmultiplied clocks from a single PLL assures that the clocks are in proper phase relationship so that the serial inputting or outputting, and the parallel loading or unloading, are properly synchronized.

    摘要翻译： 用于可编程逻辑器件的LVDS接口使用锁相环（“PLL”）电路为数据输入和输出提供数据时钟。 PLL时钟是高精度的，每个包括一个乘以W的计数器，以便可以使用倍增和非乘法时钟。 倍增时钟用于将数据串行时移到或移出移位寄存器链。 非乘法时钟用于并行加载或读取移位寄存器链中的寄存器。 从单个PLL提供相乘和非乘法时钟确保时钟处于正确的相位关系，以便串行输入或输出以及并行加载或卸载被正确同步。