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公开(公告)号：US20060043487A1
公开(公告)日：2006-03-02
申请号：US10926916
申请日：2004-08-26
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
摘要翻译： 一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR） 节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器 的第二晶体管响应于正的ESD电压而触发。
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公开(公告)号：US08890248B2
公开(公告)日：2014-11-18
申请号：US10926916
申请日：2004-08-26
申请人： Timothy Patrick Pauletti , Sameer Pendharkar , Wayne Tien-Feng Chen , Jonathan Brodsky , Robert Steinhoff
发明人： Timothy Patrick Pauletti , Sameer Pendharkar , Wayne Tien-Feng Chen , Jonathan Brodsky , Robert Steinhoff
IPC分类号： H01L23/62 , H01L29/74 , H01L27/02 , H01L29/87 , H01L29/749
CPC分类号： H01L27/0262 , H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.
摘要翻译： 一种用于保护电路的输入/输出端子的静电放电（ESD）装置，该装置包括：第一晶体管，其具有耦合在电路的输入/输出（I / O）端子之间的集成硅控整流器（SCR） 节点和第二晶体管，其具有耦合在所述节点和电源电压的负端子之间的集成硅控整流器，其中所述第一晶体管的所述硅控整流器响应于ESD ESD电压而触发，并且所述可硅可控整流器 的第二晶体管响应于正的ESD电压而触发。
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3.发明申请System and method for making a LDMOS device with electrostatic discharge protection 有权制造具有静电放电保护功能的LDMOS器件的系统和方法公开(公告)号：US20060186467A1
公开(公告)日：2006-08-24
申请号：US11063312
申请日：2005-02-21
IPC分类号： H01L29/76
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译： 半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。 每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区， 第二导电类型。 每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。 阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。
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4.发明申请MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication 有权具有集成衬底注入防护罩的MOS ESD CDM夹具及其制造方法公开(公告)号：US20050007216A1
公开(公告)日：2005-01-13
申请号：US10609920
申请日：2003-06-30
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01P1/20
CPC分类号： H01L29/0692 , H01L27/0266 , H01L29/4238
摘要： The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).
摘要翻译： 本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。 环形N型源极区域（106）通常围绕漏极区域（104）。 源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。 环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。 环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。
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5.发明授权Electrostatic discharge protection circuit having buffer stage FET with thicker gate oxide than common-source FET 有权具有比共源FET更厚的栅极氧化物的缓冲级FET的静电放电保护电路公开(公告)号：US08804290B2
公开(公告)日：2014-08-12
申请号：US13351395
申请日：2012-01-17
申请人： Jonathan Brodsky
发明人： Jonathan Brodsky
IPC分类号： H02H9/04
CPC分类号： H01L27/0281 , H01L21/823462 , H02H9/046
摘要： An active-FET ESD cell (300) for protecting an I/O pad (301) includes a first MOS transistor (310) with a gate oxide (315) of a first thickness and a second MOS transistor (320) with a gate oxide (325) of a second thickness greater than the first thickness at least by the amount required to handle the source-follower threshold voltage, the first transistor having its drain (313) tied to the I/O pad, its source (311) tied to ground, and its gate (312) tied to the source (321) of the second transistor and resistively connected to ground (340), and the second transistor having its drain (323) tied to the I/O pad and its gate tied to a capacitor (330) connected to the I/O pad and to a resistor (331) connected to ground.
摘要翻译： 用于保护I / O焊盘（301）的有源FET ESD单元（300）包括具有第一厚度的栅极氧化物（315）和具有栅极氧化物的第二MOS晶体管（320）的第一MOS晶体管（310） 至少具有处理所述源极跟随器阈值电压所需的量的第二厚度大于所述第一厚度的第二厚度（325），所述第一晶体管的漏极（313）连接到所述I / O焊盘，其源极（311） 并且其栅极（312）连接到第二晶体管的源极（321）并且电阻地连接到地（340），并且第二晶体管的漏极（323）连接到I / O焊盘并且其栅极连接 连接到连接到I / O焊盘的电容器（330）和连接到地的电阻器（331）。
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6.发明申请Electrostatic Discharge Protection Circuit Having Buffer Stage FET with Thicker Gate Oxide than Common-Source FET 有权具有比公共源FET更薄的栅氧化物的缓冲级FET的静电放电保护电路公开(公告)号：US20130182357A1
公开(公告)日：2013-07-18
申请号：US13351395
申请日：2012-01-17
申请人： Jonathan Brodsky
发明人： Jonathan Brodsky
IPC分类号： H02H9/04
CPC分类号： H01L27/0281 , H01L21/823462 , H02H9/046
摘要： An active-FET ESD cell (300) for protecting an I/O pad (301) includes a first MOS transistor (310) with a gate oxide (315) of a first thickness and a second MOS transistor (320) with a gate oxide (325) of a second thickness greater than the first thickness at least by the amount required to handle the source-follower threshold voltage, the first transistor having its drain (313) tied to the I/O pad, its source (311) tied to ground, and its gate (312) tied to the source (321) of the second transistor and resistively connected to ground (340), and the second transistor having its drain (323) tied to the I/O pad and its gate tied to a capacitor (330) connected to the I/O pad and to a resistor (331) connected to ground.
摘要翻译： 用于保护I / O焊盘（301）的有源FET ESD单元（300）包括具有第一厚度的栅极氧化物（315）和具有栅极氧化物的第二MOS晶体管（320）的第一MOS晶体管（310） 至少具有处理所述源极跟随器阈值电压所需的量的第二厚度大于所述第一厚度的第二厚度（325），所述第一晶体管的漏极（313）连接到所述I / O焊盘，其源极（311） 并且其栅极（312）连接到第二晶体管的源极（321）并且电阻地连接到地（340），并且第二晶体管的漏极（323）连接到I / O焊盘并且其栅极连接 连接到连接到I / O焊盘的电容器（330）和连接到地的电阻器（331）。
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公开(公告)号：US06784496B1
公开(公告)日：2004-08-31
申请号：US09668999
申请日：2000-09-25
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.
摘要翻译： 集成在接口电路中的CDM钳位电路，它在集成电路上进行保护。 通常，集成的CDM钳位电路和接口电路彼此相邻并且共享公共器件元件或元件，因此不需要金属互连。 因为没有互连，寄生电阻和电感也被最小化或从电路中消除，从而减少或消除过大的电压降。 优选地，CDM钳位电路通过使两个电路共享相同的硅源区域而被集成到其正在保护的电路中。 在优选实施例的输入电路中，相同的扩散区域是输入晶体管及其相关联的CDM钳位晶体管的源极。
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8.发明申请Apparatus and method for reducing leakage between an input terminal and power rail 有权用于减少输入端子和电源轨道之间的泄漏的装置和方法公开(公告)号：US20070091526A1
公开(公告)日：2007-04-26
申请号：US11257839
申请日：2005-10-25
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0255
摘要： An apparatus for reducing current leakage between an input locus and at least one power rail for a system includes, for each respective power rail: (a) A first diode unit coupled between the input locus and a coupling locus. The first diode unit is configured to effect substantially zero potential drop during normal operation of the apparatus. (b) A second diode unit coupled between the coupling locus and the respective power rail. The second diode unit is configured to present no forward bias during normal operation of the apparatus. The first and second diode units cooperate to effect current flow between the input locus and the respective power rail during a predetermined operational condition of the apparatus.
摘要翻译： 用于减少用于系统的输入轨迹和至少一个电源轨之间的电流泄漏的装置包括：对于每个相应的电源轨道：（a）耦合在输入轨迹和耦合轨迹之间的第一二极管单元。 第一二极管单元被配置为在设备的正常操作期间实质上为零的电位降。 （b）耦合在耦合轨迹和相应电力轨之间的第二二极管单元。 第二二极管单元被配置为在设备的正常操作期间不呈现正向偏压。 第一和第二二极管单元协作以在设备的预定操作状态期间在输入轨迹和相应的电力轨道之间实现电流流动。
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9.发明授权MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication 有权具有集成衬底注入防护罩的MOS ESD CDM夹具及其制造方法公开(公告)号：US06940131B2
公开(公告)日：2005-09-06
申请号：US10609920
申请日：2003-06-30
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01L23/62
CPC分类号： H01L29/0692 , H01L27/0266 , H01L29/4238
摘要： The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).
摘要翻译： 本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。 环形N型源极区域（106）通常围绕漏极区域（104）。 源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。 环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。 环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。
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10.发明授权公开(公告)号：US06919603B2
公开(公告)日：2005-07-19
申请号：US10426448
申请日：2003-04-30
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H03K19/003 , H01L23/62
CPC分类号： H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a first polarity, by a bipolar transistor (4C) formed in an n-well (64; 164), having a collector contact (72; 172) to one signal terminal (PIN1) and its emitter region (68; 168) and base (66; 166) connected to a second signal terminal (PIN2). For reverse polarity ESD protection, a diode (25) is formed in the same n-well (64; 164) by a p+ region (78; 178) connected to the second signal terminal (PIN2), serving as the anode. The cathode can correspond to the n-well (64; 164) itself, as contacted by the collector contact (72; 172). By using the same n-well (64; 164) for both devices, the integrated circuit chip area required to implement this pin-to-pin protection is much reduced.
摘要翻译： 公开了一种用于防止信号端子之间的ESD事件的静电放电（ESD）保护结构。 通过形成在n阱（64; 164）中的双极晶体管（4C）提供ESD保护，其具有到一个信号端子（PIN 1）的集电极触点（72; 172）及其发射极区域 （68; 168）和连接到第二信号端子（PIN 2）的基座（66; 166）。 对于反极性ESD保护，二极管（25）由连接到用作阳极的第二信号端子（PIN2）的p +区（78; 178）形成在同一个n阱（64; 164）中。 阴极可以与收集器触点（72; 172）接触的n阱（64; 164）本身对应。 通过对两个器件使用相同的n阱（64; 164），实现此引脚到引脚保护所需的集成电路芯片面积大大减少。
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