利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

47 条记录 (耗时 0.037 秒)

    Efficient data-directed scrambler for noise-shaping mixed-signal converters
    1.
    发明授权
    Efficient data-directed scrambler for noise-shaping mixed-signal converters 有权
    用于噪声整形混合信号转换器的高效数据导向扰频器

    公开(公告)号：US07205913B2

    公开(公告)日：2007-04-17

    申请号：US10127903

    申请日：2002-04-23

    申请人： Robert W. Adams ,  Douglas J. Mar ,  M. K. Stephen Yeung

    发明人： Robert W. Adams ,  Douglas J. Mar ,  M. K. Stephen Yeung

    IPC分类号： H03M5/00

    CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/464 ,  H03M3/502

    摘要： An efficient data-directed scrambler is provided for processing digital signals having an unequally-weighted code. The data-directed scrambler includes inputs for receiving unequally-weighted bits of an input signal, outputs for supplying N scrambled bits of an output signal, and two or more scrambler columns connected in series between the inputs and the outputs. One or more of the scrambler columns includes a swapper cell and a digital fanout. Least significant bits in the unequally-weighted code are input to a swapper cell, and higher order bits in the unequally-weighted code are input to respective digital fanouts. In the other embodiments, an efficient data-directed scrambler is provided for processing digital signals having an equally-weighted code.

    摘要翻译： 提供了一种用于处理具有不等加权码的数字信号的有效数据导向扰频器。 数据导向扰频器包括用于接收输入信号的不均衡加权比特的输入，用于提供输出信号的N个加扰比特的输出和串联连接在输入和输出之间的两个或更多个扰频列。 一个或多个扰频器列包括交换单元和数字扇出。 不平等加权码中的最低有效位被输入到交换单元，并且将不平等加权代码中的较高阶位输入到相应的数字扇出。 在其他实施例中，提供了一种有效的数据导向扰频器，用于处理具有同等加权码的数字信号。

    Data-directed scrambler for noise-shaping mixed-signal converters with an arbitrary number of quantization levels
    2.
    发明授权
    Data-directed scrambler for noise-shaping mixed-signal converters with an arbitrary number of quantization levels 有权
    用于具有任意数量级量化的噪声整形混合信号转换器的数据导向扰频器

    公开(公告)号：US06614377B1

    公开(公告)日：2003-09-02

    申请号：US10071603

    申请日：2002-02-08

    申请人： Robert W. Adams ,  Douglas J. Mar ,  M. K. Stephen Yeung

    发明人： Robert W. Adams ,  Douglas J. Mar ,  M. K. Stephen Yeung

    IPC分类号： H03M166

    CPC分类号： H03M1/0665 ,  H03M1/747 ,  H03M3/464

    摘要： Methods and apparatus are provided for processing N equally-weighted digital signals, where N is an arbitrary integer not necessarily an integer power of 2. The methods and apparatus are particularly useful in noise-shaping, mixed-signal converters. The apparatus includes a rotator for rotating the N equally-weighted digital signals in a sequence of rotator states in respective clock cycles to provide N rotated digital signals, and a data-directed scrambler having N inputs and N outputs for data-directed scrambling of the rotated digital signals to distribute the N equally-weighted digital signals to each of the N outputs of the scrambler such that the usage of the N outputs is dynamically balanced over a relatively small number of clock cycles, leading to a shaped noise spectrum.

    摘要翻译： 提供了用于处理N个等权重数字信号的方法和装置，其中N是不必要的整数2的任意整数。该方法和装置在噪声整形混合信号转换器中特别有用。 该装置包括一个旋转器，用于以相应时钟周期的旋转器状态的顺序旋转N个等加权的数字信号，以提供N个旋转的数字信号;以及数据导向的加扰器，具有N个输入和N个输出，用于数据导向的加扰 旋转数字信号以将N个等重加权的数字信号分配给加扰器的N个输出中的每一个，使得N个输出的使用在相对较少数量的时钟周期上动态平衡，导致成形的噪声谱。

    Hybrid tuning circuit for continuous-time sigma-delta analog-to-digital converter
    5.
    发明授权
    Hybrid tuning circuit for continuous-time sigma-delta analog-to-digital converter 有权
    用于连续时间Σ-Δ模数转换器的混合调谐电路

    公开(公告)号：US07095345B2

    公开(公告)日：2006-08-22

    申请号：US10936179

    申请日：2004-09-08

    申请人： Khiem Nguyen ,  Robert W. Adams

    发明人： Khiem Nguyen ,  Robert W. Adams

    IPC分类号： H03M1/10

    CPC分类号： H03M3/386 ,  H03J1/0091 ,  H03J2200/10 ,  H03M3/458

    摘要： A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

    摘要翻译： 使用混合调谐电路，包括数字有限状态机和模拟调谐电路，以有效地保持连续时间积分器的RC乘积在过程，温度，电源和采样率变化之间恒定。 由于实施是连续的，跟踪比传统技术更准确。 使用精心挑选的时钟方案，该技术消除了反馈DAC中的符号间干扰。 该技术不使用参考频率，从而消除了用户识别参考频率的需要。

    Asynchronous digital sample rate converter
    6.
    发明授权
    Asynchronous digital sample rate converter 失效
    异步数字采样率转换器

    公开(公告)号：US6141671A

    公开(公告)日：2000-10-31

    申请号：US653125

    申请日：1996-05-24

    申请人： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

    发明人： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

    IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  G06F17/17

    CPC分类号： H03H17/0628

    摘要： An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

    摘要翻译： 异步数字采样率转换器包括用于存储输入数据值的随机存取存储器和用于存储缩减的一组内插滤波器系数的只读存储器。 输入数据以输入采样率写入随机存取存储器。 输出样本由给定输入数据流的乘法/累加引擎提供，滤波器系数根据请求在输出频率下产生输出采样。 用于从随机存取存储器读取输入数据的初始地址和来自只读存储器的系数的地址由自动定心方案提供，该自动定心方案是具有通过输入的近似馈送的数字积分器的一阶闭环系统 输出采样率。 这种自动对中方案可以包括用于消除稳态误差的前馈低通滤波器和内插写入地址以减少噪声。 还可以提供确定输入到输入采样速率比的电路，以缩放系数地址和产生的输出采样以允许抽取。 该电路包括一种消除噪声的数字滞后形式。 通过依赖于内插滤波器的脉冲响应的对称性以及利用可变步长前后线性插值来减小ROM系数。

    Lid and lid system for storing an implement in a container
    7.
    发明授权
    Lid and lid system for storing an implement in a container 失效
    用于将工具存储在容器中的盖和盖系统

    公开(公告)号：US6041919A

    公开(公告)日：2000-03-28

    申请号：US221105

    申请日：1998-12-23

    申请人： Robert W. Adams

    发明人： Robert W. Adams

    IPC分类号： A45D34/04 ,  B44D3/12 ,  A45D44/18

    CPC分类号： B44D3/127 ,  A45D34/046

    摘要： A lid for a container having a spreadable fluid therein. The lid includes a less resilient portion having at least one hole defined therethrough and at least one more resilient portion overlapping the at least one hole of the less resilient portion. The more resilient portion has at least one slit grouping in registration with the at least one hole of the less resilient portion. The at least one slit grouping perforates the more resilient material.

    摘要翻译： 用于其中具有可展开流体的容器的盖子。 盖子包括弹性较小的部分，其具有穿过其中限定的至少一个孔，并且至少一个弹性部分与较小弹性部分的至少一个孔重叠。 更具弹性的部分具有至少一个与较小弹性部分的至少一个孔对准的狭缝组。 至少一个狭缝组穿透更有弹性的材料。

    Digital sample rate converters having matched group delay
    9.
    发明授权
    Digital sample rate converters having matched group delay 有权

    公开(公告)号：US06531970B2

    公开(公告)日：2003-03-11

    申请号：US09876468

    申请日：2001-06-07

    申请人： Kevin J McLaughlin ,  Robert W. Adams

    发明人： Kevin J McLaughlin ,  Robert W. Adams

    IPC分类号： H03M700

    CPC分类号： H03H17/0628

    摘要： Methods and apparatus are provided for sample rate conversion in a system including two or more sample rate converters. The method includes the steps of providing an input clock and an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master. The measured sample rate ratio may be transmitted from the master to each of the other sample rate converters. This approach matches the group delays among the sample rate converters.

    Digital-to-analog converter using noise-shaped segmentation
    10.
    发明授权
    Digital-to-analog converter using noise-shaped segmentation 失效
    数字模拟转换器采用噪声分割

    公开(公告)号：US5977899A

    公开(公告)日：1999-11-02

    申请号：US936752

    申请日：1997-09-25

    申请人： Robert W. Adams

    发明人： Robert W. Adams

    IPC分类号： H03M3/04 ,  H03M7/16 ,  H03M3/00

    CPC分类号： H03M7/165 ,  H03M3/50 ,  H03M1/066 ,  H03M7/3015 ,  H03M7/3026 ,  H03M7/3042

    摘要： A segmentation circuit includes a digital noise shaper responsive to a stream of digital input words for producing a stream of first digital subwords, and a subtractor for subtracting each of the first digital subwords from a corresponding one of the digital input words to produce a stream of second digital subwords that are noise-shaped. The first and second digital subwords have smaller word lengths than the digital input words. The sum of each of the first and second subwords is equal to the corresponding digital input word. When the digital input words are noise-shaped, the first and second digital subwords are both noise-shaped. The segmentation circuit may be used in a noise-shaping digital-to-analog converter having a multi-bit loop quantizer.

    摘要翻译： 分割电路包括响应于用于产生第一数字子字词流的数字输入字的流的数字噪声整形器，以及用于从数字输入字中的相应一个减去每个第一数字子词的减法器，以产生流 第二个数字子词是噪音形状。 第一和第二数字子词具有比数字输入字更小的字长。 第一和第二子词中的每一个的和等于相应的数字输入字。 当数字输入字是噪声形状时，第一和第二数字子词都是噪声形的。 分割电路可以用在具有多位环路量化器的噪声整形数模转换器中。