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1.发明授权MOS transistor gates with thin lower metal silicide and methods for making the same 有权具有薄的下金属硅化物的MOS晶体管栅极及其制造方法公开(公告)号：US07045456B2
公开(公告)日：2006-05-16
申请号：US10745454
申请日：2003-12-22
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
摘要翻译： 呈现用于制造晶体管栅极结构的方法，其中上和下金属硅化物形成在栅极电介质上方。 在一个示例中，下硅化物通过在栅极电介质上沉积薄的第一含硅材料而形成，其被注入，然后通过退火与第一金属反应以形成下硅化物。 在退火之前可以在第一金属上形成覆盖层，以防止在硅化物之前金属的氧化，并且可以在下硅化物上形成阻挡层以防止随后形成的硅材料的反应。 在另一个实例中，下硅化物是包括多个金属硅化物层的多层硅化物结构。
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公开(公告)号：US07470577B2
公开(公告)日：2008-12-30
申请号：US11204235
申请日：2005-08-15
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译： 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。
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3.发明申请公开(公告)号：US20080157228A1
公开(公告)日：2008-07-03
申请号：US11618650
申请日：2006-12-29
CPC分类号： H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495
摘要： Exemplary embodiments provide structures and fabrication methods for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.
摘要翻译： 示例性实施例提供了用于双功能金属栅电极的结构和制造方法。 通过在金属/电介质界面处设置各种电负性物质和/或正电性物质来控制界面偶极子，可以增加和/或降低金属栅电极的功函数值。 在示例性实施例中，各种电负性物质可以设置在金属/电介质界面处以增加金属的功函数值，其可用于双功能门控器件中的PMOS金属栅电极。 可以在金属/电介质界面处设置各种正电性物质，以降低金属的功函数值，这可以用于双功能门控器件中的NMOS金属栅电极。
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4.发明授权Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏公开(公告)号：US07176076B2
公开(公告)日：2007-02-13
申请号：US11118843
申请日：2005-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。
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公开(公告)号：US07842567B2
公开(公告)日：2010-11-30
申请号：US12271080
申请日：2008-11-14
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译： 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。
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6.发明授权Method for fabricating split gate transistor device having high-k dielectrics 有权具有高k电介质的分离栅晶体管器件的制造方法公开(公告)号：US06979623B2
公开(公告)日：2005-12-27
申请号：US10738957
申请日：2003-12-17
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.
摘要翻译： 公开了通过制造具有在半导体器件的不同区域中具有可选厚度的栅极电介质的晶体管器件来促进半导体制造的方法和系统。 厚度对应于相应的晶体管器件的工作电压。 此外，本发明还提供了可以制造具有高k电介质材料的栅极电介质的系统和方法，其允许比常规二氧化硅更厚的栅极电介质。
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7.发明授权Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing 有权双层沉积以避免在高K栅介质处理期间的不希望的界面反应公开(公告)号：US06696332B2
公开(公告)日：2004-02-24
申请号：US10176596
申请日：2002-06-21
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/2652 , H01L21/28194 , H01L21/28202 , H01L21/28238 , H01L21/28291 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.
摘要翻译： 公开了用于形成用于MOSFET晶体管的栅极电介质的方法，其中使用氮化物层和氧化物层的双层沉积来形成栅极电介质叠层。 在衬底上形成氮化物层以防止氧化物层沉积期间衬底材料的氧化，从而避免或减轻低k界面层的形成。
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公开(公告)号：US07601577B2
公开(公告)日：2009-10-13
申请号：US11870631
申请日：2007-10-11
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。
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9.发明授权Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS silicon oxynitride dielectric formation using direct nitridation of silicon 有权半导体CMOS器件和方法与NMOS高k电介质之间形成核心PMOS氮氧化硅介质形成之前，采用直接氮化硅公开(公告)号：US07351632B2
公开(公告)日：2008-04-01
申请号：US11118842
申请日：2005-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L27/105 , H01L21/823842 , H01L21/823857 , H01L27/11 , H01L27/1116
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.
摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成氧化物层。 氧化物层从器件的核心区域移除（508）。 在芯和I / O区域上形成高k电介质层（510）。 然后，从芯和I / O区域的PMOS区域去除高k电介质层（512）。 通过低温热处理在核心和I / O区域的PMOS区域内生长氮化硅层（516）。 随后，进行氧化处理（518），其将氮化硅氧化成氮氧化硅。
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10.发明授权Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏公开(公告)号：US07642146B2
公开(公告)日：2010-01-05
申请号：US11620447
申请日：2007-01-05
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。
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