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1.发明授权Method for fabricating split gate transistor device having high-k dielectrics 有权具有高k电介质的分离栅晶体管器件的制造方法公开(公告)号：US06979623B2
公开(公告)日：2005-12-27
申请号：US10738957
申请日：2003-12-17
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L29/51
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： Methods and systems are disclosed that facilitate semiconductor fabrication by fabricating transistor devices having gate dielectrics with selectable thicknesses in different regions of semiconductor devices. The thicknesses correspond to operating voltages of the corresponding transistor devices. Furthermore, the present invention also provides systems and methods that can fabricate the gate dielectrics with high-k dielectric material, which allows a thicker gate dielectric than conventional silicon dioxide.
摘要翻译： 公开了通过制造具有在半导体器件的不同区域中具有可选厚度的栅极电介质的晶体管器件来促进半导体制造的方法和系统。 厚度对应于相应的晶体管器件的工作电压。 此外，本发明还提供了可以制造具有高k电介质材料的栅极电介质的系统和方法，其允许比常规二氧化硅更厚的栅极电介质。
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2.发明授权Method for fabricating transistor gate structures and gate dielectrics thereof 有权制造晶体管栅极结构及其栅极电介质的方法公开(公告)号：US07135361B2
公开(公告)日：2006-11-14
申请号：US10734708
申请日：2003-12-11
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。
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公开(公告)号：US06852645B2
公开(公告)日：2005-02-08
申请号：US10367429
申请日：2003-02-13
IPC分类号： C23C28/00 , H01L21/02 , H01L21/28 , H01L21/316 , H01L29/51 , H01L29/78 , H01L21/469
CPC分类号： H01L21/28185 , C23C28/00 , H01L21/02238 , H01L21/02255 , H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/31155 , H01L21/31662 , H01L21/31691 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention pertains to methods for forming high quality thin interface oxide layers suitable for use with high-k gate dielectrics in the manufacture of semiconductor devices. An ambient that contains oxygen and a reducing agent is utilized to grow the layers. The oxygen facilitates growth of the layers, while the reducing agent simultaneously counteracts that growth. The rate of growth of the layers can thus be controlled by regulating the partial pressure of the reducing agent, which is the fraction of the reducing agent in the gas phase times the total pressure. Controlling and slowing the growth rate of the layers facilitates production of the layers to thicknesses of about 10 Angstroms or less at temperatures of about 850 degrees Celsius or more. Growing the layers at high temperatures facilitates better bonding and production of higher quality layers, which in turn yields better performing and more reliable resulting products.
摘要翻译： 本发明涉及在制造半导体器件时形成适用于高k栅极电介质的高品质薄界面氧化物层的方法。 使用含有氧和还原剂的环境来生长层。 氧促进层的生长，而还原剂同时抵消该生长。 因此，可以通过调节还原剂的分压来控制层的生长速度，还原剂的分压是气相中还原剂的分数乘以总压力。 控制和减缓层的生长速率有助于在约850摄氏度或更高的温度下将层的生产达到约10埃或更小的厚度。 在高温下生长层有助于更好地粘合和生产更高质量的层，这又产生更好的性能和更可靠的结果产品。
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公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译： 一种改善高卡门电介质膜（104）性能的方法。 对高卡帕膜（104）进行两步退火处理。 第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。 第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。
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5.发明授权High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权具有均匀氮分布的高k栅极电介质及其制造方法公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译： 提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。
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6.发明授权Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures 有权使用氧化剂/氢混合物退火超薄，高质量的栅氧化层的方法公开(公告)号：US06780719B2
公开(公告)日：2004-08-24
申请号：US09885744
申请日：2001-06-20
申请人： Hiroaki Niimi , Rajesh Khamankar , James J. Chambers , Sunil Hattangady , Antonio L. P. Rotondaro
发明人： Hiroaki Niimi , Rajesh Khamankar , James J. Chambers , Sunil Hattangady , Antonio L. P. Rotondaro
IPC分类号： H01L21336
CPC分类号： H01L21/02332 , H01L21/0214 , H01L21/02164 , H01L21/02323 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L29/518
摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.
摘要翻译： 本发明的一个实施例是形成超薄介电层的方法，该方法包括以下步骤：提供具有半导体表面的基板; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自四种再氧化技术：在H2和N2的混合物中连续退火 （优选小于20％H 2），然后是O 2和N 2（优选小于20％O 2）的混合物;通过尖峰状升温（优选在1000至1150℃下优选小于1秒）在氮气中退火 （优选为N 2 / O 2或N 2 O / H 2）;通过在减压的氨中快速热加热（优选在600至1000℃下5至60秒）进行退火;在氧化剂/氢气混合物（优选N 2 O 1％H 2）在800至1050℃下进行5至60秒。
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7.发明申请公开(公告)号：US20120164820A1
公开(公告)日：2012-06-28
申请号：US13404840
申请日：2012-02-24
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译： 本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向 进行氢退火。
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8.发明授权公开(公告)号：US08124529B2
公开(公告)日：2012-02-28
申请号：US11421671
申请日：2006-06-01
IPC分类号： H01L21/44
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译： 本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向 进行氢退火。
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公开(公告)号：US07528024B2
公开(公告)日：2009-05-05
申请号：US10890365
申请日：2004-07-13
IPC分类号： H01L21/28 , H01L21/338 , H01L21/44
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
摘要翻译： 本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。 该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。 金属层的功函数与半导体衬底的导带或价带相匹配。 该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。 对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。 本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。
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公开(公告)号：US06936508B2
公开(公告)日：2005-08-30
申请号：US10661130
申请日：2003-09-12
申请人： Mark Visokay , Luigi Colombo , James J. Chambers
发明人： Mark Visokay , Luigi Colombo , James J. Chambers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/3205 , H01L29/76
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/513 , H01L29/517 , H01L29/665
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.
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