公开(公告)号：US06175913B1

公开(公告)日：2001-01-16

申请号：US08928768

申请日：1997-09-12

申请人： Eric Chesters ,  Roger D. Arnold ,  Rod G. Fleck

发明人： Eric Chesters ,  Roger D. Arnold ,  Rod G. Fleck

IPC分类号： G06F1500

CPC分类号： G06F11/3636 ,  G06F11/3656

摘要： A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.

摘要翻译： 描述了一种数据处理单元，其包括中央处理单元，与中央处理单元耦合的总线，以经由与总线耦合的地址和数据线访问设备。 调试单元耦合到总线，保护单元与总线和调试单元耦合，用于保护总线上的访问。 保护单元可编程为在保护模式下工作，其中总线可以被保护，并且在调制模式中，信号被发送到调试单元，于是调试单元产生调试信号。

公开(公告)号：US06434689B1

公开(公告)日：2002-08-13

申请号：US09189111

申请日：1998-11-09

申请人： Rod G. Fleck ,  Roger D. Arnold ,  Bruce Holmer ,  Danielle G. Lemay

发明人： Rod G. Fleck ,  Roger D. Arnold ,  Bruce Holmer ,  Danielle G. Lemay

IPC分类号： G06F1500

摘要： An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.

公开(公告)号：US6128641A

公开(公告)日：2000-10-03

申请号：US928252

申请日：1997-09-12

申请人： Rod G. Fleck ,  Roger D. Arnold ,  Bruce Holmer ,  Vojin G. Oklobdzija ,  Eric Chesters

发明人： Rod G. Fleck ,  Roger D. Arnold ,  Bruce Holmer ,  Vojin G. Oklobdzija ,  Eric Chesters

IPC分类号： G06F9/30 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/30054 ,  G06F9/462

摘要： The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save area. The memory is coupled with the register file and an instruction control unit with a program counter register and a program status word register coupled with the memory and the register file. The method comprises the steps of acquiring a new save area from said unused save area, storing the context of the first task in said new area, linking the new area with said previous context save area.

摘要翻译： 本发明涉及一种在具有多个通用寄存器和上下文切换寄存器的寄存器文件的数据处理单元中的从第一任务到第二任务的上下文切换的方法，包括先前的上下文保存区域的存储器和 未使用的上下文保存区域。 存储器与寄存器文件和具有程序计数器寄存器的指令控制单元和与存储器和寄存器文件耦合的程序状态字寄存器耦合。 该方法包括以下步骤：从所述未使用的保存区域获取新的保存区域，将第一任务的上下文存储在所述新区域中，将新区域与所述先前的上下文保存区域相链接。

公开(公告)号：US06292845B1

公开(公告)日：2001-09-18

申请号：US09140474

申请日：1998-08-26

申请人： Rod G. Fleck ,  Bruce Holmer ,  Ole H. Møller ,  Roger D. Arnold ,  Balraj Singh

发明人： Rod G. Fleck ,  Bruce Holmer ,  Ole H. Møller ,  Roger D. Arnold ,  Balraj Singh

IPC分类号： G06F930

CPC分类号： G06F9/3822 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3816 ,  G06F9/3836

摘要： An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each instruction contains at least a single bit indicating said instruction sizes. An instruction buffer coupled with an instruction size evaluation unit for determining the instruction size upon said at least single bit of said instruction is provided.

摘要翻译： 描述用于从由数据处理设备处理的存储器加载指令的指令获取单元。 指令代码可以具有至少两个不同的长度，并且每个指令至少包含指示所述指令大小的单个位。 提供与指令大小评估单元耦合的指令缓冲器，用于在所述指令的所述至少一个位上确定指令大小。

公开(公告)号：US6041387A

公开(公告)日：2000-03-21

申请号：US928428

申请日：1997-09-12

申请人： Rod G. Fleck ,  Roger D. Arnold

发明人： Rod G. Fleck ,  Roger D. Arnold

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00

CPC分类号： G06F9/30032 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30141 ,  G06F9/3885

摘要： A data processing unit has a set of data registers and a set of address registers. Each register has a width of n bits. Furthermore, there are provided address load and store buffers associated with the address registers, data load and store buffers associated with the data registers and a bus having a plurality of bus lines being connected to the store buffers. A data memory unit is connected to the bus. The data registers are arranged in such a way that at least n data registers are connected in parallel to respective bus lines, n being greater than 1, and the address registers are arranged in such a way, that at least m address registers are coupled in parallel to respective bus lines, m being greater than 1. Thus, at least four registers can be accessed in parallel.

摘要翻译： 数据处理单元具有一组数据寄存器和一组地址寄存器。 每个寄存器的宽度为n位。 此外，提供了与数据寄存器相关联的地址寄存器，数据加载和存储缓冲器相关联的地址负载和存储缓冲器以及连接到存储缓冲器的多条总线线路的总线。 数据存储单元连接到总线。 数据寄存器被布置成使得至少n个数据寄存器并行连接到相应的总线，n大于1，并且地址寄存器以这样的方式布置，至少m个地址寄存器耦合在 平行于各个总线，m大于1.因此，可以并行访问至少四个寄存器。

公开(公告)号：US06378065B1

公开(公告)日：2002-04-23

申请号：US09069030

申请日：1998-04-27

申请人： Roger D. Arnold ,  Alfred Eder

发明人： Roger D. Arnold ,  Alfred Eder

IPC分类号： G06F900

CPC分类号： G06F9/30141 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/462 ,  G11C7/00

摘要： The present invention relates to a data processing unit, comprising at least one register having at least one read port and one write port. The register has at least two memory cells each having a write line and a read line, a first switch having inputs and one output for coupling said read line of one of said memory cells with said read port, second switch for coupling said write line of one of said memory cells with said write port.

摘要翻译： 本发明涉及一种数据处理单元，包括至少一个具有至少一个读端口和一个写端口的寄存器。 寄存器具有至少两个具有写入线和读取线的存储器单元，具有输入的第一开关和用于将所述存储器单元之一的所述读取线与所述读取端口耦合的第一开关，用于将所述写入线 所述存储单元中的一个具有所述写入端口。

公开(公告)号：US07047396B1

公开(公告)日：2006-05-16

申请号：US09888295

申请日：2001-06-22

申请人： David A. Fotland ,  Roger D. Arnold ,  Tibet Mimaroglu

发明人： David A. Fotland ,  Roger D. Arnold ,  Tibet Mimaroglu

IPC分类号： G06F7/38

CPC分类号： G06F9/3016 ,  G06F7/49994 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3812

摘要： A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.

摘要翻译： 一种固定长度存储器到存储器处理固定长度指令的方法和系统。 此外，本发明是用于实现与ALU宽度无关的存储器操作数宽度的方法和系统。 算术和寄存器数据是32位，但存储器操作数的大小是可变的。 存储器操作数的大小由指令指定。 根据本发明的指令允许在单个固定长度指令中的多个存储器操作数。 指令集小而简单，所以执行成本比传统处理器低。 提供了更多的寻址模式，从而创建了更有效的代码。 信号量使用单个位实现。 移位和合并指令用于访问跨越边界的数据。

公开(公告)号：US07360203B2

公开(公告)日：2008-04-15

申请号：US10774193

申请日：2004-02-06

申请人： Robert E. Ober ,  Daniel F. Martin ,  Roger D. Arnold ,  Erik K. Norden

发明人： Robert E. Ober ,  Daniel F. Martin ,  Roger D. Arnold ,  Erik K. Norden

IPC分类号： G06F9/45

CPC分类号： G06F9/3851 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3861

摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.

摘要翻译： 多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。 线程ID附加到获取位集合的指令和操作数。 多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。 线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。

公开(公告)号：US06859873B2

公开(公告)日：2005-02-22

申请号：US09878145

申请日：2001-06-08

申请人： Erik K. Norden ,  Roger D. Arnold ,  Robert E. Ober ,  Neil S. Hastie

发明人： Erik K. Norden ,  Roger D. Arnold ,  Robert E. Ober ,  Neil S. Hastie

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3824 ,  G06F9/3867

摘要： A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.

公开(公告)号：US4583725A

公开(公告)日：1986-04-22

申请号：US708403

申请日：1985-03-05

申请人： Roger D. Arnold

发明人： Roger D. Arnold

IPC分类号： A61G13/12 ,  A61G13/00

CPC分类号： A61G13/12 ,  A61G13/0054 ,  A61G13/123 ,  A61G2200/325

摘要： A patient support frame for use on an operating table during posterior lumbar laminectomy surgery comprises a frame for attachment to said table and a pair of iliac crest supports slidably mounted on said frame. The iliac crest supports are adjustable to engage the iliacs, or hipbones, of the patient whereby the prone patient is supported so that the abdomen does not touch the table and is substantially without pressure thereon.

摘要翻译： 在后腰椎板切除手术期间用于手术台的患者支撑框架包括用于附接到所述桌子的框架和可滑动地安装在所述框架上的一对髂骨顶部支撑件。 髂嵴支撑是可调节的，以接合患者的髂骨或髋骨，由此倾斜患者被支撑，使得腹部不接触桌子并且基本上没有压力。