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1.发明授权Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation 失效具有LCD控制的微控制器可更新RAM存储数据，从而确定LCD像素激活
公开(公告)号：US6031510A
公开(公告)日：2000-02-29
申请号：US671950
申请日：1996-06-28
Applicant: Rodney Drake , Scott Ellison
Inventor： Rodney Drake , Scott Ellison
CPC classification number: G09G3/18 , G09G2330/02
Abstract: Method and apparatus for controlling the updating of a random access memory (RAM) that stores data for coding the activation of segments of one or more alphanmeric characters of a liquid crystal display (LCD), to maintain substantially a direct current (DC) voltage value of zero across transparent conductive plates of the LCD, is performed or provided in a microcontroller having internal LCD control capabilities. A type B waveform is employed for activating the LCD, the waveform being of a type in which data is transmitted over two frames, the data in the second frame of which is the inverse of data in the first frame thereof to maintain an average DC voltage value over each two-frame portion of the waveform at substantially zero volt. The RAM is allowed to be written to for updating the data therein only after completion of an entire two-frame portion of the waveform and before commencement of a new two-frame portion, to avoid a non-zero average DC voltage across the LCD glass during a two-frame portion. An error bit is set whenever an attempt is made to write to the RAM at times other than between the end of a two-frame portion and the commencement of a new two-frame portion. A response to the error bit is made by returning to the write step that prompted it, to determine whether all of the data intended to be written has been stored in the RAM.
Abstract translation: 用于控制随机存取存储器（RAM）的更新的方法和装置，其存储用于对液晶显示器（LCD）的一个或多个字母字符的段的激活进行编码的数据，以维持基本上直流（DC）电压值 在LCD的透明导电板上的零位被执行或提供在具有内部LCD控制能力的微控制器中。 采用B型波形来激活LCD，该波形是数据在两帧上传输的类型，第二帧中的数据是其第一帧中的数据的倒数，以保持平均DC电压 波形的每个两帧部分基本上为零伏。 在完成波形的整个两帧部分之后并且在新的两帧部分开始之前，允许RAM被写入以用于更新其中的数据，以避免LCD玻璃上的非零平均DC电压 在两帧部分。 每当尝试在两帧部分的结束之前的时间和新的两帧部分的开始之间的时间尝试写入RAM时，设置错误位。 通过返回提示它的写入步骤来确定对错误位的响应，以确定所有要写入的数据是否已经存储在RAM中。
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2.发明授权Microcontroller chip with integrated LCD control module and switched capacitor driver circuit 失效具有集成LCD控制模块和开关电容驱动电路的微控制器芯片
公开(公告)号：US5861861A
公开(公告)日：1999-01-19
申请号：US671575
申请日：1996-06-28
Applicant: James B. Nolan , Scott Ellison , Brian Boles , Rodney Drake , Russell E. Cooper
Inventor： James B. Nolan , Scott Ellison , Brian Boles , Rodney Drake , Russell E. Cooper
Abstract: Apparatus for providing multiple of discrete voltage levels to drive a liquid crystal display (LCD) from an LCD module on board a microcontroller chip includes a charge pump with a switched-capacitor that develops the discrete voltages as multiples of the value of a base voltage that remains substantially without change irrespective of change in the supply voltage. A switched-capacitor charging circuit selectively charges a capacitor to produce successive additive charges individually retrievable from the capacitor. An LCD drive selectively transmits the discrete voltage levels to activate the LCD according to status of an external system under the control of the microcontroller. Voltage losses that may occur during the switched-capacitor charging are compensated to maintain the levels of the discrete voltages free of decay. Compensation is achieved by overcharging the capacitor by an amount substantially equivalent to the amount of voltage loss on the capacitor, using active feedback obtained from monitoring the charge on the capacitor.
Abstract translation: 用于提供多个离散电压电平以从微控制器芯片上的LCD模块驱动液晶显示器（LCD）的装置包括具有开关电容器的电荷泵，其将离散电压开发为基本电压值的倍数 无论电源电压的变化如何，均保持基本无变化。 开关电容器充电电路选择性地对电容器充电以产生可从电容器单独检索的连续的附加电荷。 LCD驱动器根据微控制器的控制，根据外部系统的状态选择性地发送离散电压电平以激活LCD。 在开关电容器充电期间可能发生的电压损耗被补偿以保持离散电压的电平没有衰减。 通过使用从监视电容器上的电荷获得的有效反馈，使电容器过充电达到与电容器上的电压损失量相当的量。
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公开(公告)号：US11941632B2
公开(公告)日：2024-03-26
申请号：US16597371
申请日：2019-10-09
Applicant: Dyron Clower , John Templer , La Shonna Sharp , Aaron Calipari , Michael Ring , Michael Serrette , Nickolas Ledford , Lawrence Dugger , Rodney Drake , Diana Hayes
Inventor： Dyron Clower , John Templer , La Shonna Sharp , Aaron Calipari , Michael Ring , Michael Serrette , Nickolas Ledford , Lawrence Dugger , Rodney Drake , Diana Hayes
CPC classification number: G06Q20/4016 , G06Q20/108 , G06Q2220/00
Abstract: A real-time system and method for invoking a fraud alert notification to a bank prompted by an abandoned deposit following a denied accelerated funding request for a financial item.
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公开(公告)号：US06552567B1
公开(公告)日：2003-04-22
申请号：US09964664
申请日：2001-09-28
Applicant: Brian Boles , Richard Fischer , Sumit Mitra , Rodney Drake , Stephen A. Bowling , Bryan Kris , Steven Marsh , Hassan Harb
Inventor： Brian Boles , Richard Fischer , Sumit Mitra , Rodney Drake , Stephen A. Bowling , Bryan Kris , Steven Marsh , Hassan Harb
IPC: H03K190175
CPC classification number: G06F15/76
Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.
Abstract translation: 本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。 更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。 更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。
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5.发明授权Method for powering down unused configuration bits to minimize power consumption 有权关闭未使用配置位以最小化功耗的方法公开(公告)号：US06463544B2
公开(公告)日：2002-10-08
申请号：US09850214
申请日：2001-05-07
Applicant: Joseph W. Triece , Rodney Drake , Igor Wojewoda
Inventor： Joseph W. Triece , Rodney Drake , Igor Wojewoda
IPC: G06F126
CPC classification number: G11C5/14 , G11C7/1045 , H03K19/0016
Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.
Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。
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Patent Agency Ranking
公开(公告)号：US20200082407A1
公开(公告)日：2020-03-12
申请号：US16597371
申请日：2019-10-09
Applicant: Dyron Clower , John Templer , La Shonna Sharp , Aaron Calipari , Michael Ring , Michael Serrette , Nickolas Ledford , Lawrence Dugger , Rodney Drake , Diana Hayes
Inventor： Dyron Clower , John Templer , La Shonna Sharp , Aaron Calipari , Michael Ring , Michael Serrette , Nickolas Ledford , Lawrence Dugger , Rodney Drake , Diana Hayes
Abstract: A real-time system and method for invoking a fraud alert notification to a bank prompted by an abandoned deposit following a denied accelerated funding request for a financial item.
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公开(公告)号：US20050166036A1
公开(公告)日：2005-07-28
申请号：US10969338
申请日：2004-10-19
Applicant: Michael Catherwood , Edward Boles , Stephen Bowling , Joshua Conner , Rodney Drake , John Elliott , Brian Fall , James Grosbach , Tracy Kuhrt , Guy McCarthy , Manuel Muro , Mike Pyska , Joseph Triece
Inventor： Michael Catherwood , Edward Boles , Stephen Bowling , Joshua Conner , Rodney Drake , John Elliott , Brian Fall , James Grosbach , Tracy Kuhrt , Guy McCarthy , Manuel Muro , Mike Pyska , Joseph Triece
CPC classification number: G06F9/3885 , G06F9/30014 , G06F9/30145 , G06F9/30167 , G06F9/325 , G06F9/3893
Abstract: An instruction set is provided that features multiple instructions and various address modes to deliver a mixture of flexible microcontroller-like instructions and specialized digital signal processing (“DSP”) execute instructions from a single instruction stream. A subset of instructions of the instruction set can be executed by a processor. Similarly, another subset of the instructions can be utilized by the digital signal processor. A software application can thus take advantage of digital signal processing capabilities in the same program, obviating the need for separate programs for separate processors.
Abstract translation: 提供了一种指令集，其具有多个指令和各种地址模式，以提供灵活的类似微控制器的指令和专用数字信号处理（“DSP”）的混合从单个指令流执行指令。 指令集的指令子集可由处理器执行。 类似地，数字信号处理器可以利用指令的另一子集。 因此，软件应用程序可以利用同一程序中的数字信号处理能力，从而避免对单独处理器的单独程序的需要。
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公开(公告)号：US06708268B1
公开(公告)日：2004-03-16
申请号：US09280112
申请日：1999-03-26
Applicant: Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
Inventor： Edward Brian Boles , Rodney Drake , Darrel Johansen , Sumit Mitra , Joseph Triece , Randy Yach
IPC: G06F1208
CPC classification number: G06F9/30192 , G06F9/30032 , G06F9/3004 , G06F9/30101 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/321 , G06F9/325
Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.
Abstract translation: 微控制器装置设置有用于操纵微控制器的行为的指令集。 提供了使得能够实现模块化仿真的线性化地址空间的装置和系统。 可以通过寄存器文件或数据存储器进行直接或间接寻址。 特殊功能寄存器，包括程序计数器（PC）和工作寄存器（W），映射到数据存储器中。 正交（对称）指令集可以使用任何寻址模式对任何寄存器进行任何操作。 因此，在两个操作数指令中要使用两个文件寄存器。 这允许在两个寄存器之间直接移动数据，而不经过W寄存器。 从而提高性能并减少程序内存的使用。
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公开(公告)号：US20170270496A1
公开(公告)日：2017-09-21
申请号：US15602058
申请日：2017-05-22
Applicant: Dyron Clower , John Templer , La Shonna Sharp , Aaron Calipari , Michael Ring , Michael Serrette , Nickolas Ledford , Lawrence Dugger , Rodney Drake , Diana Hayes
Inventor： Dyron Clower , John Templer , La Shonna Sharp , Aaron Calipari , Michael Ring , Michael Serrette , Nickolas Ledford , Lawrence Dugger , Rodney Drake , Diana Hayes
IPC: G06Q20/10
CPC classification number: G06Q20/1085 , G06Q20/042 , G06Q20/3223 , G06Q20/40145 , G06Q20/4016 , G06Q20/405 , G06Q40/02
Abstract: A real-time system and method for determining whether to invoke a fraud alert notification to a bank concerning an account holder or an item issuer following an interim determination that the account holder or item issuer has participated in a fraudulent transaction. An interim determination is updated based in part on bank transaction data received following the interim determination.
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10.发明授权Circuit for powering down unused configuration bits to minimize power consumption 有权关闭未使用配置位的电路，以最大限度地降低功耗公开(公告)号：US06230275B1
公开(公告)日：2001-05-08
申请号：US09232053
申请日：1999-01-15
Applicant: Joseph W. Triece , Rodney Drake , Igor Wojewoda
Inventor： Joseph W. Triece , Rodney Drake , Igor Wojewoda
IPC: G06F126
CPC classification number: G11C5/14 , G11C7/1045 , H03K19/0016
Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.
Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。
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