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10 条记录 (耗时 0.036 秒)

    Data communication flow control device and methods thereof
    8.
    发明授权
    Data communication flow control device and methods thereof 有权

    公开(公告)号：US07457892B2

    公开(公告)日：2008-11-25

    申请号：US11446891

    申请日：2006-06-05

    申请人： James E. Innis ,  Iftekhar Ahmed ,  Matthew Joseph Taylor ,  David W. Todd

    发明人： James E. Innis ,  Iftekhar Ahmed ,  Matthew Joseph Taylor ,  David W. Todd

    IPC分类号： G06F3/00

    CPC分类号： G06F5/12 ,  G06F2205/126

    摘要： A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

    Data communication flow control device and methods thereof
    9.
    发明申请
    Data communication flow control device and methods thereof 有权
    数据通信流量控制装置及其方法

    公开(公告)号：US20080005405A1

    公开(公告)日：2008-01-03

    申请号：US11446891

    申请日：2006-06-05

    申请人： James E. Innis ,  Iftekhar Ahmed ,  Matthew Joseph Taylor ,  David W. Todd

    发明人： James E. Innis ,  Iftekhar Ahmed ,  Matthew Joseph Taylor ,  David W. Todd

    IPC分类号： G06F3/00

    CPC分类号： G06F5/12 ,  G06F2205/126

    摘要： A device for controlling data communication flow to a data buffer of an integrated circuit is disclosed. The device receives data communicated from a transmitting device. The received data is placed in a data buffer in memory. The data buffer is defined by a set of buffer descriptors, whereby a number of free buffer descriptors in the set of buffer descriptors is indicative of the amount of free space in the data buffer. A communications controller determines whether the data buffer is subject to overflowing by determining when the number of free buffer descriptors moves below a threshold level (a watermark). The communications controller sends a request to the transmitting device to stop transmitting data in response to determining that the data buffer is possibly subject to an overflow condition, indicating that the data buffer is nearly full.

    摘要翻译： 公开了一种用于控制到集成电路的数据缓冲器的数据通信流的设备。 设备接收从发送设备传送的数据。 接收的数据被放置在存储器中的数据缓冲器中。 数据缓冲器由一组缓冲器描述符定义，其中该组缓冲器描述符中的多个空闲缓冲器描述符指示数据缓冲器中的可用空间量。 通信控制器通过确定空闲缓冲器描述符的数量何时移动到阈值水平以下（水印）来确定数据缓冲器是否被溢出。 响应于确定数据缓冲器可能经受溢出状态，指示数据缓冲器几乎已满，通信控制器向发送设备发送请求以停止发送数据。

    High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations
    10.
    发明授权
    High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations 失效
    在支持多级缓存组织的超标量微处理器中高性能地执行负载预留指令

    公开(公告)号：US5835946A

    公开(公告)日：1998-11-10

    申请号：US634907

    申请日：1996-04-18

    申请人： Michael S. Allen ,  Brad B. Beavers ,  Robert Alan Cargnoni ,  Jose Melanio Nunez ,  David W. Todd ,  Jen-Tian Yen

    发明人： Michael S. Allen ,  Brad B. Beavers ,  Robert Alan Cargnoni ,  Jose Melanio Nunez ,  David W. Todd ,  Jen-Tian Yen

    IPC分类号： G06F9/312 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F9/3004 ,  G06F12/0875 ,  G06F9/30087 ,  G06F12/0897

    摘要： The present invention provides a system and method for efficient execution of load reserve (LARX) and store conditional (STCX) instructions in a superscalar processor. A system for efficiently providing a LARX instruction in a superscalar processor is disclosed. The system comprises a data cache (Dcache) for receiving the LARX instruction. The data cache further includes a decoder means for setting and resetting of a validation of the load reserve instruction, an internal cache for receiving address information and for providing data. The system also includes a register means for receiving the LARX instruction and a controller means for providing a physical address based upon the address information. The system provides for the validation being accomplished in one cycle for the LARX instruction when there is a hit on the internal data cache.

    摘要翻译： 本发明提供了一种用于在超标量处理器中有效执行负载储备（LARX）和存储条件（STCX）指令的系统和方法。 公开了一种用于在超标量处理器中有效提供LARX指令的系统。 该系统包括用于接收LARX指令的数据高速缓存（Dcache）。 数据高速缓存还包括用于设置和重置负载保留指令的验证的解码器装置，用于接收地址信息并用于提供数据的内部高速缓存。 该系统还包括用于接收LARX指令的寄存器装置和用于基于地址信息提供物理地址的控制器装置。 当在内部数据高速缓存上存在命中时，系统提供在LARX指令的一个周期内完成的验证。