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    High-K metal gate electrode structures formed by early cap layer adaptation
    1.
    发明授权
    High-K metal gate electrode structures formed by early cap layer adaptation 有权
    通过早期盖层适应形成的高K金属栅电极结构

    公开(公告)号：US08664057B2

    公开(公告)日：2014-03-04

    申请号：US13565970

    申请日：2012-08-03

    申请人： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    发明人： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/28 ,  H01L21/44 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

    摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

    摘要翻译： 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION
    2.
    发明申请
    HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY EARLY CAP LAYER ADAPTATION 有权
    高K金属电极结构由早期盖层适应形成

    公开(公告)号：US20130034942A1

    公开(公告)日：2013-02-07

    申请号：US13565970

    申请日：2012-08-03

    申请人： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    发明人： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

    摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

    摘要翻译： 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

    Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method
    7.
    发明授权
    Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method 有权
    具有背面源极/漏极接触插头的半导体晶体管器件结构及相关制造方法

    公开(公告)号：US08373228B2

    公开(公告)日：2013-02-12

    申请号：US12687607

    申请日：2010-01-14

    申请人： Bin Yang ,  Rohit Pal ,  Michael Hargrove

    发明人： Bin Yang ,  Rohit Pal ,  Michael Hargrove

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/12 ,  H01L27/1211

    摘要： A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

    摘要翻译： 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

    SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES AND NON-FETS WITH DIFFERENT HEIGHT BY EARLY ADAPTATION OF GATE STACK TOPOGRAPHY
    8.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES AND NON-FETS WITH DIFFERENT HEIGHT BY EARLY ADAPTATION OF GATE STACK TOPOGRAPHY 审中-公开
    包含金属栅极电极结构和不同高度的非FET的半导体器件通过栅格堆叠拓扑的早期适应

    公开(公告)号：US20130032893A1

    公开(公告)日：2013-02-07

    申请号：US13550693

    申请日：2012-07-17

    申请人： Rohit Pal ,  George Mulfinger

    发明人： Rohit Pal ,  George Mulfinger

    IPC分类号： H01L27/088 ,  H01L21/283

    CPC分类号： H01L23/5256 ,  H01L23/485 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Gate height scaling in sophisticated semiconductor devices may be implemented without requiring a redesign of non-transistor devices. To this end, the semiconductor electrode material may be adapted in its thickness above active regions and isolation regions that receive the non-transistor devices. Thereafter, the actual patterning of the adapted gate layer stack may be performed so as to obtain gate electrode structures of a desired height for improving, in particular, AC performance without requiring a redesign of the non-transistor devices.

    摘要翻译： 可以实现复杂半导体器件中的栅极高度缩放，而不需要重新设计非晶体管器件。 为此，可以将半导体电极材料的厚度适用于有源区域和接收非晶体管器件的隔离区域。 此后，可以执行适合的栅极层堆叠的实际图案化，以获得所需高度的栅电极结构，以改善特别是AC性能，而不需要重新设计非晶体管器件。

    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
    10.
    发明授权
    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
    用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法

    公开(公告)号：US08217463B2

    公开(公告)日：2012-07-10

    申请号：US13021403

    申请日：2011-02-04

    申请人： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

    发明人： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

    摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

    摘要翻译： 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。