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    Apparatus and process for sampling a serial digital signal
    1.
    发明授权
    Apparatus and process for sampling a serial digital signal 失效
    串行数字信号采样的装置和处理

    公开(公告)号：US5848109A

    公开(公告)日：1998-12-08

    申请号：US510458

    申请日：1995-08-02

    申请人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

    发明人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

    IPC分类号： H04L7/00 ,  H04L7/033 ,  H03B3/04

    CPC分类号： H04L7/0337 ,  H04L7/0029

    摘要： A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

    摘要翻译： 一种用于对串行数字信号（D）进行采样的处理和装置，其包括用时钟信号（C）对数字信号进行定相并在延迟时刻（Si）对数字信号进行采样，其中定相参照 抽样时刻。 定相包括确定参考采样时刻（Si）的相位测试时刻（Pi），以验证数字信号的转换是相对于定相测试时刻是在前进还是相位滞后。 定相测试时刻的确定是通过将​​延迟Y = kR / 2加到每个采样时刻（Si）来实现的，其中k是除零之外的正整数奇数，R表示 数字信号（D）。 本发明在数据处理和远程数据处理系统以及电信系统中具有特别的用途。

    Frequency multiplier using XOR/NXOR gates which have equal propagation delays
    3.
    发明授权
    Frequency multiplier using XOR/NXOR gates which have equal propagation delays 失效
    使用具有相等传播延迟的XOR / NXOR门的倍频器

    公开(公告)号：US5614841A

    公开(公告)日：1997-03-25

    申请号：US362892

    申请日：1994-12-23

    申请人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

    发明人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Reza Nezamzadeh-Moosavi

    IPC分类号： H01L21/8234 ,  H01L27/088 ,  H03K5/00 ,  H03K19/21

    CPC分类号： H03K19/215 ,  H03K5/00006

    摘要： The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

    摘要翻译： 具有两个输入（A，B）的异或类型的门（11）以树形结构设置在从接收树的输入信号的输入层开始的集成电路的连续层中。 每个栅极的输出端连接到相邻层中的栅极的输入端。 每个门包括两个单元（11a，11b），其响应于来自两个输入中的一个的两个相应的互补信号（A，NA; B，NB）而基本同时地切换，并提供表示互补功能的各个输出信号 XOR，NXOR）的OR类型。 这使得可以获得完全相等的传播时间，无论树的活动输入或要传播的边缘的传播时间完全相等，无论树的活动输入或要传播的边缘可以是什么。

    Variable-delay circuit
    4.
    发明授权
    Variable-delay circuit 失效
    可变延迟电路

    公开(公告)号：US5327031A

    公开(公告)日：1994-07-05

    申请号：US47545

    申请日：1993-03-08

    申请人： Roland Marbot ,  Andrew Cofler ,  Michel Combes ,  Jean-Claude Lebihan ,  Reza Nezamzadeh-Moosavi

    发明人： Roland Marbot ,  Andrew Cofler ,  Michel Combes ,  Jean-Claude Lebihan ,  Reza Nezamzadeh-Moosavi

    IPC分类号： H03K5/00 ,  H03K5/13

    CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00065 ,  H03K2005/00195

    摘要： A variable delay circuit including a fixed delay circuit (D1) furnishing a signal (e.sub.1) that is delayed with respect to the input signal (e.sub.0). A combination circuit (C) furnishes a combination signal (f.sub.K) resulting from the superposition, with weighting and an integral effect of the input (e.sub.0) and delayed (e.sub.1) signals. The assembly is dimensioned such that the fixed delay (T) is less than the transition time that the combination signal (f.sub.K) has when only the input signal (e.sub.0) is applied.

    摘要翻译： 一种可变延迟电路，包括提供相对于输入信号（e0）被延迟的信号（e1）的固定延迟电路（D1）。 组合电路（C）提供由叠加产生的组合信号（fK）与加权和输入（e0）和延迟（e1）信号的积分效应。 组件的尺寸使得固定延迟（T）小于当仅施加输入信号（e0）时组合信号（fK）具有的转变时间。