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1.发明授权Digital communications modulator having a modulation processor which supports high data rates 失效具有支持高数据速率的调制处理器的数字通信调制器公开(公告)号：US06337606B1
公开(公告)日：2002-01-08
申请号：US09241697
申请日：1999-02-02
IPC分类号： H04L2720
CPC分类号： H04L25/03834 , H04L27/2071
摘要： An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).
摘要翻译： IC调制处理器（28）可以被配置为以单芯片模式操作以适应处理器（28）的最大时钟速率的波特率，并且以双芯片模式适应超过最大时钟速率的波特率 。 IC调制处理器（28）对传送输入数据流（22）的通信信号执行数字处理。 在相位映射器（50）之后提供脉冲整形滤波器（54-57）。 脉冲整形滤波器（54-57）被实现为一对半滤波器。 在双芯片模式下，脉冲整形分布在两个IC调制处理器（28）之间。 内插器（86）和线性化器（106）跟随脉冲整形滤波器（54-57）。
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2.发明授权
公开(公告)号：US6128282A
公开(公告)日：2000-10-03
申请号：US994002
申请日：1997-12-18
CPC分类号： H04Q11/0478 , H04L2012/5612
摘要： A node controller (30) within a data communication network (22) provides network access for a digital data stream (32). A processor (42) partitions the digital data stream (32) into a constant data rate component (44) having a predictable data rate and a data packet component (46) having an unpredictable data rate. The constant data rate component (44) is then transferred over a first portion (74) of a network data stream (26) reserved for a circuit transmission protocol, and the data packet component (46) is packetized and transferred over a second portion (76) of the network data stream (26) reserved for a packet transmission protocol.
摘要翻译： 数据通信网络（22）内的节点控制器（30）为数字数据流（32）提供网络接入。 处理器（42）将数字数据流（32）分割成具有可预测数据速率的恒定数据速率分量（44）和具有不可预测数据速率的数据分组分量（46）。 恒定数据速率分量（44）然后通过为电路传输协议保留的网络数据流（26）的第一部分（74）传送，并且数据分组组件（46）被分组化并在第二部分 76）被保留用于分组传输协议的网络数据流（26）。
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公开(公告)号：US5671257A
公开(公告)日：1997-09-23
申请号：US468921
申请日：1995-06-06
CPC分类号： H04L7/0054 , H03L7/087 , H04L7/0334 , H03L7/091 , H04L7/0083
摘要： A digital communication receiver (10) takes one complex sample (20) of a baseband analog signal (12) per symbol. A rectangular to polar converter (26) separates phase attributes of the complex samples from magnitude attributes. A phase processor (28) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (32) influences symbol timing only during clock adjustment opportunities. The magnitude processor (32) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities. An interpolator (66) may be used to estimate magnitude values between samples so that magnitude change is determined between sampled magnitude values and estimated magnitude values.
摘要翻译： 数字通信接收机（10）每个符号采用基带模拟信号（12）的一个复样本（20）。 矩形到极化转换器（26）将复数样本的相位属性与幅度属性分开。 相位处理器（28）识别在相邻符号之间发生相对大的相位变化时发生的时钟调整机会。 幅度处理器（32）仅在时钟调整机会期间影响符号定时。 当在时钟调整机会期间检测到减小的幅度变化时，幅度处理器（32）在锁相环中提前符号定时，并且在时钟调整机会期间检测到增加幅度变化时延迟符号定时。 可以使用内插器（66）来估计样本之间的幅度值，使得在采样的幅度值和估计的幅度值之间确定幅度变化。
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公开(公告)号：US4531224A
公开(公告)日：1985-07-23
申请号：US507193
申请日：1983-06-23
IPC分类号： H04L7/027 , H04L27/00 , H04L27/227 , H03D3/06 , H04L7/02
CPC分类号： H04L7/0274 , H04L27/2273 , H04L2027/0067
摘要： A low SNR symbol synchronizer utilizes two quadrature channels and a delay and multiply technique to produce four product signals. Two of the product signals are same-channel products and two are cross-channel products. When combined and applied to a synchronizing apparatus such as a Costas loop, the signals provide improved performance at low SNR and avoid the need to know the carrier frequency when setting the delay.
摘要翻译： 低SNR符号同步器利用两个正交信道和延迟和乘法技术来产生四个乘积信号。 两个产品信号是同频道产品，另外两个是交叉通道产品。 当组合并应用于诸如科斯塔斯环路的同步装置时，该信号在低SNR下提供改进的性能，并且避免在设置延迟时知道载波频率。
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5.发明授权
公开(公告)号：US4486846A
公开(公告)日：1984-12-04
申请号：US392852
申请日：1982-06-28
CPC分类号： G06F1/0356 , G06F2101/04
摘要： A numerically controlled oscillator wherein only one quadrant of a sinusoidially shaped wave is stored in a read-only-memory and the address of the read-only-memory is generated so that the entire numerically controlled oscillator and the read-only memory are contained on a single semiconductor chip. The data required to reproduce the quadrant is stored in a decomposed format so as to reduce the size of the read-only-memory.
摘要翻译： 一个数控振荡器，其中只有一个正弦形波的一个象限被存储在只读存储器中，并且产生只读存储器的地址，使得整个数控振荡器和只读存储器被包含在 单个半导体芯片。 复制象限所需的数据以分解格式存储，以减小只读存储器的大小。
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6.再颁专利公开(公告)号：USRE41380E1
公开(公告)日：2010-06-15
申请号：US10718507
申请日：2003-11-19
CPC分类号： H04L25/03834 , H04B1/717 , H04B1/719 , H04B2201/70706 , H04L27/2614 , H04L27/2627 , H04L27/3411 , H04L27/3494 , H04L27/363
摘要： A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies the constrained-envelope signal stream (112) and transmits it as a radio-frequency broadcast signal (26).
摘要翻译： 一种限制包络数字通信发射机电路（22），其中二进制数据源（32）提供输入信号流（34），相位映射器（44）将输入信号流（34）映射到正交相位点 信号流（50），每单位波特间隔（64）具有预定数量的符号，并且在相位点星座（46）中定义相位点（54），脉冲扩展滤波器（76）对相位点信号 流（50）转换成经滤波的信号流（74），约束包络发生器（106）从经滤波的信号流（74）产生约束带宽误差信号流（108），延迟元件（138） 信号流（74）转换成与受约束带宽误差信号流（108）同步的延迟信号流（140），复数求和电路（110）将延迟信号流（140）和约束带宽误差信号流 108）到约束包络信号流（112）中，并且基本上是线性的 放大器（146）放大约束包络信号流（112）并将其作为射频广播信号（26）发送。
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公开(公告)号：US06366619B1
公开(公告)日：2002-04-02
申请号：US09635990
申请日：2000-08-09
IPC分类号： H04L2704
CPC分类号： H04L25/03834 , H04B1/707 , H04B1/717 , H04B1/719 , H04B2201/70706 , H04L27/2614 , H04L27/2627 , H04L27/3411 , H04L27/3494 , H04L27/363
摘要： A constrained-envelope digital-communications transmitter circuit (22) includes a binary data source (32) that provides an input signal stream (34) to a modulator (77,77′). The modulator (77,77′) includes a pulse-spreading filter (76) that filters a phase-point signal stream (50) or a composite signal stream (168) into a modulated signal (74). A constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the modulated signal (74), and a delay element (138) delays the modulated signal (74) into a delayed modulated signal (140) synchronized with the constrained-bandwidth error signal stream (108). A complex summing circuit (110) sums the delayed modulated signal (140) and the constrained-bandwidth error signal stream (108) into an altered modulated signal (112), and a substantially linear amplifier (146) amplifies the altered modulated signal (112) and transmits it as a radio-frequency broadcast signal (26).
摘要翻译： 约束包络数字通信发射机电路（22）包括向调制器（77,77'）提供输入信号流（34）的二进制数据源（32）。 调制器（77,77'）包括将相位信号流（50）或复合信号流（168）过滤成调制信号（74）的脉冲扩展滤波器（76）。 约束包络发生器（106）从调制信号（74）产生约束带宽误差信号流（108），延迟元件（138）将调制信号（74）延迟到延迟调制信号（140）同步 与约束带宽误差信号流（108）。 复数求和电路（110）将延迟的调制信号（140）和约束带宽误差信号流（108）合并为改变的调制信号（112），并且基本上线性的放大器（146）放大改变的调制信号（112 ）并将其作为射频广播信号（26）发送。
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8.发明授权
公开(公告)号：US6154510A
公开(公告)日：2000-11-28
申请号：US303845
申请日：1999-05-03
CPC分类号： H04L7/0062 , H03L7/091 , H04L7/007 , H04L7/0029
摘要： A digital communication receiver (10) includes a magnitude-based symbol synchronizer (38) which separates complex phase attributes from magnitude attributes. The phase attributes are processed by a phase processor (78) which identifies clock adjustment opportunities. The magnitude attributes are processed by a magnitude processor (76) that generates a phase error estimate signal (82), which in turn drives a clock generator (24) in a phase locked loop (54) to achieve symbol synchronization in a non-data-directed manner. An additional adjustment feedback loop (114, 128) includes a phase error offset generator (52) and operates in conjunction with the phase locked loop (54) to allow the phase locked loop (54) to achieve lock and a robust operating point in spite of distortion in a received input analog signal (12).
摘要翻译： 数字通信接收机（10）包括基于幅度的符号同步器（38），其将复杂相位属性与幅度属性分离。 相位属性由识别时钟调整机会的相位处理器（78）来处理。 大小属性由产生相位误差估计信号（82）的幅度处理器（76）处理，相位误差估计信号又驱动锁相环（54）中的时钟发生器（24）以实现非数据中的符号同步 指向的方式。 附加调整反馈回路（114,128）包括相位误差偏移发生器（52）并且与锁相环（54）一起操作，以允许锁相环（54）尽可能实现锁定和鲁棒的工作点 在接收的输入模拟信号（12）中产生失真。
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9.发明授权
公开(公告)号：US6104761A
公开(公告)日：2000-08-15
申请号：US143230
申请日：1998-08-28
CPC分类号： H04L25/03834 , H04B1/717 , H04L27/3411 , H04L27/3494 , H04L27/363 , H04B1/719 , H04B2201/70706 , H04L27/2614 , H04L27/2627
摘要： A constrained-envelope digital-communications transmitter circuit (22) in which a binary data source (32) provides an input signal stream (34), a phase mapper (44) maps the input signal stream (34) into a quadrature phase-point signal stream (50) having a predetermined number of symbols per unit baud interval (64) and defining a phase point (54) in a phase-point constellation (46), a pulse-spreading filter (76) filters the phase-point signal stream (50) into a filtered signal stream (74), a constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the filtered signal stream (74), a delay element (138) delays the filtered signal stream (74) into a delayed signal stream (140) synchronized with the constrained-bandwidth error signal stream (108), a complex summing circuit (110) sums the delayed signal stream (140) and the constrained-bandwidth error signal stream (108) into a constrained-envelope signal stream (112), and a substantially linear amplifier (146) amplifies the constrained-envelope signal stream (112) and transmits it as a radio-frequency broadcast signal (26).
摘要翻译： 一种限制包络数字通信发射机电路（22），其中二进制数据源（32）提供输入信号流（34），相位映射器（44）将输入信号流（34）映射到正交相位点 信号流（50），每单位波特间隔（64）具有预定数量的符号，并且在相位点星座（46）中定义相位点（54），脉冲扩展滤波器（76）对相位点信号 流（50）转换成经滤波的信号流（74），约束包络发生器（106）从经滤波的信号流（74）产生约束带宽误差信号流（108），延迟元件（138） 信号流（74）转换成与受约束带宽误差信号流（108）同步的延迟信号流（140），复数求和电路（110）将延迟信号流（140）和约束带宽误差信号流 108）到约束包络信号流（112）中，并且基本上是线性的 放大器（146）放大约束包络信号流（112）并将其作为射频广播信号（26）发送。
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公开(公告)号：US6041088A
公开(公告)日：2000-03-21
申请号：US95357
申请日：1998-06-10
CPC分类号： H04W56/0035 , H04W84/14 , H04L1/0026 , H04W92/10
摘要： Different subscriber units (14) transmit different burst signals to a base station (12) on a common frequency to which a base station demodulator (64) is already synchronized. The base station (12) transmits constant values .alpha. and .eta., where .alpha. is multiplied by a base station reference frequency to achieve a base station transmitting frequency, and .eta. is multiplied by the reference frequency to achieve the base station (12) receiving frequency. A subscriber unit (14) synchronizes to the base station transmitting frequency. As a result of the synchronization process, the subscriber unit (14) determines a value .mu., which, when multiplied by a subscriber unit reference frequency, achieves the subscriber unit synchronization frequency. The subscriber unit then determines a value .gamma., which is proportional to .eta. and .beta. and inversely proportional to .alpha.. The subscriber unit reference frequency is multiplied by .gamma. to achieve the frequency at which the subscriber unit (14) transmits.
摘要翻译： 不同的用户单元（14）在基站解调器（64）已经同步的公共频率上向基站（12）发送不同的突发信号。 基站（12）发送常数α和eta，其中α乘以基站参考频率以实现基站发射频率，并且eta乘以参考频率以实现基站（12）接收频率。 用户单元（14）与基站发射频率同步。 作为同步处理的结果，用户单元（14）确定一个值mu，当与用户单元参考频率相乘时，它实现用户单元同步频率。 订户单元然后确定一个值γ，其与eta和β成正比并与α成反比。 将用户单元参考频率乘以伽马，以实现用户单元（14）发送的频率。
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