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    Apparatus and method for testing semiconductors
    1.
    发明授权
    Apparatus and method for testing semiconductors 失效
    用于半导体测试的装置和方法

    公开(公告)号：US06836106B1

    公开(公告)日：2004-12-28

    申请号：US10668561

    申请日：2003-09-23

    申请人： Kevin H. Brelsford ,  Ronald G. Filippi, Jr. ,  Kenneth P. Rodbell ,  Ping-Chuan Wang

    发明人： Kevin H. Brelsford ,  Ronald G. Filippi, Jr. ,  Kenneth P. Rodbell ,  Ping-Chuan Wang

    IPC分类号： G01R3126

    CPC分类号： G11C29/56 ,  G01R31/2858 ,  G11C29/1201 ,  G11C2029/5602

    摘要： A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.

    摘要翻译： 用于测试半导体的测试电路包括多个至少第一导体和第二导体。 第一和第二导体通过多个导电通孔可操作地连接在一起以形成交替的第一和第二导体的开链。 包括多个导电抽头，每个抽头在第一端连接到对应的第一导体。 测试电路还包括多个开关电路，每个开关电路可操作地连接到对应的一个导电抽头的第二端。 响应于呈现给开关电路的至少一个控制信号，每个开关电路可配置为有选择地将对应的导电抽头连接到至少第一总线和第二总线中的一个，第一和第二总线连接到第一和第二总线 第二接合垫。

    Ionizing radiation blocking in IC chip to reduce soft errors
    2.
    发明授权
    Ionizing radiation blocking in IC chip to reduce soft errors 有权
    IC芯片中的电离辐射阻断减少软错误

    公开(公告)号：US08999764B2

    公开(公告)日：2015-04-07

    申请号：US11836819

    申请日：2007-08-10

    申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

    发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

    IPC分类号： H01L21/00 ,  H01L23/532 ,  H01L23/556

    CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

    摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

    摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

    Computer program products for determining stopping powers of design structures with respect to a traveling particle
    5.
    发明授权
    Computer program products for determining stopping powers of design structures with respect to a traveling particle 有权
    用于确定相对于旅行颗粒的设计结构的停止力的计算机程序产品

    公开(公告)号：US07877716B2

    公开(公告)日：2011-01-25

    申请号：US12111529

    申请日：2008-04-29

    申请人： Giovanni Fiorenza ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Henry Tang

    发明人： Giovanni Fiorenza ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Henry Tang

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G06G7/62

    CPC分类号： G06F17/5009 ,  G06F2217/16

    摘要： A computer program product, comprising a computer readable storage device having a computer readable program code stored therein, said program code including an algorithm adapted to be executed by a computer to implement a method. First, design information of a design structure is provided including a back-end-of-line layer of an integrated circuit which includes N interconnect layers, wherein N is a positive integer. Next, each interconnect layer is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, wherein M is a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined.

    摘要翻译： 一种计算机程序产品，包括具有存储在其中的计算机可读程序代码的计算机可读存储设备，所述程序代码包括适于由计算机执行以实现方法的算法。 首先，提供一种设计结构的设计信息，其包括包括N个互连层的集成电路的后端行层，其中N是正整数。 接下来，每个互连层被分成多个像素。 接下来，确定N个互连层的第一互连层中的行进粒子的第一路径。 接下来，识别行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，其中M是正整数。 接下来，确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。

    METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING
    8.
    发明申请
    METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING 有权
    用于加速软错误测试的方法和结构

    公开(公告)号：US20090065955A1

    公开(公告)日：2009-03-12

    申请号：US11852353

    申请日：2007-09-10

    申请人： Michael S. Gordon ,  Kenneth P. Rodbell ,  Henry H. K. Tang

    发明人： Michael S. Gordon ,  Kenneth P. Rodbell ,  Henry H. K. Tang

    IPC分类号： H01L23/48 ,  G01R31/26 ,  H01L21/4763

    CPC分类号： G01R31/2881 ,  G01R31/2858 ,  G01R31/31816 ,  H01L21/76825 ,  H01L21/84 ,  H01L23/53233 ,  H01L23/53238 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit, method of forming the integrated circuit and a method of testing the integrated circuit for soft-error fails. The integrated circuit includes: a silicon substrate; a dielectric layer formed over the substrate; electrically conductive wires formed in the dielectric layer, the wires interconnecting semiconductor devices formed in the substrate into circuits; and an alpha particle emitting region in the integrated circuit chip proximate to one or more of the semiconductor devices. The method includes exposing the integrated circuit to an artificial flux of thermal neutrons to cause fission of atoms in the alpha particle emitting region into alpha particles and other atoms.

    摘要翻译： 一种集成电路，形成集成电路的方法以及用于软错误的集成电路测试的方法失败。 集成电路包括：硅衬底; 形成在所述基板上的电介质层; 形成在电介质层中的导电线，将形成在基板中的半导体器件互连成电路的导线; 以及靠近一个或多个半导体器件的集成电路芯片中的α粒子发射区域。 该方法包括将集成电路暴露于热中子的人造通量，以使α粒子发射区中的原子裂变为α粒子和其它原子。