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    Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring
    1.
    发明授权
    Method and apparatus for accelerated determination of electromigration characteristics of semiconductor wiring 失效
    用于加速确定半导体布线的电迁移特性的方法和装置

    公开(公告)号：US06603321B2

    公开(公告)日：2003-08-05

    申请号：US09999719

    申请日：2001-10-26

    申请人： Ronald G. Filippi, Jr. ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Deborah Tibel ,  Michael Ruprecht ,  Carole Graas

    发明人： Ronald G. Filippi, Jr. ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Deborah Tibel ,  Michael Ruprecht ,  Carole Graas

    IPC分类号： G01R3126

    CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value for is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.

    摘要翻译： 公开了一种用于确定集成电路器件中的布线结构的电迁移特性的方法。 在本发明的示例性实施例中，该方法包括配置用于集成电路器件的定义的测试结构类型。 所确定的测试结构类型还包括主要布置在半导体衬底的主平面中的第一布线和连接到第一布线的第二布线。 布线的第二线设置在基本上平行于主平面的二次平面中，其中第一和第二布线通过它们之间的通孔结构连接。 确定第一线路和通孔结构的电阻的热系数，并且在限定的测试结构类型的第一单独测试结构中引入晶片级应力条件。 然后，对于第一单独测试结构确定至少一个参数值，哪个参数值用于预测集成电路器件中的布线结构的寿命投影。

    Thermo-mechanical cleavable structure
    2.
    发明授权
    Thermo-mechanical cleavable structure 有权
    热机械可切割结构

    公开(公告)号：US08018017B2

    公开(公告)日：2011-09-13

    申请号：US10905905

    申请日：2005-01-26

    申请人： Fen Chen ,  Cathryn J. Christiansen ,  Richard S. Kontra ,  Tom C. Lee ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Joseph E. Therrien

    发明人： Fen Chen ,  Cathryn J. Christiansen ,  Richard S. Kontra ,  Tom C. Lee ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Joseph E. Therrien

    IPC分类号： H01L31/058

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

    摘要翻译： 提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。 如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。 当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。 气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。 熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。 热机械应力还由于由其产生的气体引起的相变而收缩。 当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

    Enhancement of performance of a conductive wire in a multilayered substrate
    4.
    发明授权
    Enhancement of performance of a conductive wire in a multilayered substrate 失效
    提高多层基板中的导线的性能

    公开(公告)号：US07511378B2

    公开(公告)日：2009-03-31

    申请号：US11442911

    申请日：2006-05-30

    申请人： Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

    发明人： Jason P. Gill ,  David L. Harmon ,  Deborah M. Massey ,  Alvin W. Strong ,  Timothy D. Sullivan ,  Junichi Furukawa

    IPC分类号： H01L23/48

    CPC分类号： G06F17/5077 ,  H01L23/3677 ,  H01L23/522 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/0201 ,  H05K3/0005 ,  H01L2924/00

    摘要： An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

    摘要翻译： 具有布线的电子结构以及用于限制布线中的温度梯度的结构设计的相关方法。 该电子结构包括具有包括不物理接触的第一和第二线的层的衬底。 由于焦耳加热相对于第一和第二导线中的电流密度，第一和第二导线适于处于升高的温度。 第一导线通过存在于层之外的导电和导热结构电耦合到第二导线。 第二导线的宽度被调整为将第一导线中的温度梯度限制在低于预定足够小的阈值，以便基本上减轻第一线中的电迁移的不利影响。

    On-chip embedded thermal antenna for chip cooling
    7.
    发明授权
    On-chip embedded thermal antenna for chip cooling 有权
    片上嵌入式热天线芯片散热

    公开(公告)号：US08178434B2

    公开(公告)日：2012-05-15

    申请号：US13244998

    申请日：2011-09-26

    申请人： Fen Chen ,  Jeffrey P. Gambino ,  Alvin W. Strong

    发明人： Fen Chen ,  Jeffrey P. Gambino ,  Alvin W. Strong

    IPC分类号： H01L21/768

    CPC分类号： H01L23/585 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

    摘要翻译： 一种装置包括半导体芯片内的第一层，其具有与其它有源结构电连接并且具有电隔离的第一无效结构的有源结构。 半导体芯片内的第二层物理连接到第一层。 第二层包括绝缘体并具有第二非活性结构。 第一非活性结构与第二非活性结构物理对准。

    ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING
    8.
    发明申请
    ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING 有权
    芯片嵌入式热天线芯片冷却

    公开(公告)号：US20120015511A1

    公开(公告)日：2012-01-19

    申请号：US13244998

    申请日：2011-09-26

    申请人： FEN CHEN ,  Jeffrey P. Gambino ,  Alvin W. Strong

    发明人： FEN CHEN ,  Jeffrey P. Gambino ,  Alvin W. Strong

    IPC分类号： H01L21/768

    CPC分类号： H01L23/585 ,  H01L23/3677 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures.

    摘要翻译： 一种装置包括半导体芯片内的第一层，其具有与其它有源结构电连接并且具有电隔离的第一无效结构的有源结构。 半导体芯片内的第二层物理连接到第一层。 第二层包括绝缘体并具有第二非活性结构。 第一非活性结构与第二非活性结构物理对准。

    MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES
    9.
    发明申请
    MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES 失效
    统计应力的测量方法和阵列结构和可靠性结构测试

    公开(公告)号：US20100318313A1

    公开(公告)日：2010-12-16

    申请号：US12482999

    申请日：2009-06-11

    申请人： Kanak B. Agarwal ,  Nazmul Habib ,  Jerry D. Hayes ,  John G. Massey ,  Alvin W. Strong

    发明人： Kanak B. Agarwal ,  Nazmul Habib ,  Jerry D. Hayes ,  John G. Massey ,  Alvin W. Strong

    IPC分类号： G01R31/26 ,  G06F19/00

    CPC分类号： G01R31/2621 ,  G01R31/318511

    摘要： System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.

    摘要翻译： 在使用晶片级测试设备的同时，在晶片级以快速和简化的方式获得统计数据的系统和方法。 该系统和方法在给定芯片上执行所有DUT的并联应力，以保持应力时间短，然后允许对该芯片上的每个DUT进行单独测试，同时将该芯片上的其他DUT保持在应力状态，以避免任何松弛 。 在一个应用中，获得的统计数据使得能够分析晶体管器件的负温度偏置不稳定性（NTBI）现象。 虽然获得统计数据可能对于NBTI而言更为重要，因为器件缩小时其已知的行为，结构和方法以及较小的适当调整可用于强调多个DUT用于许多技术可靠性机制。

    Array-Based Early Threshold Voltage Recovery Characterization Measurement
    10.
    发明申请
    Array-Based Early Threshold Voltage Recovery Characterization Measurement 失效
    基于阵列的早期阈值电压恢复特性测量

    公开(公告)号：US20090251167A1

    公开(公告)日：2009-10-08

    申请号：US12061077

    申请日：2008-04-02

    申请人： Kanak B. Agarwal ,  Nazmul Habib ,  Jerry D. Hayes ,  John Greg Massey ,  Alvin W. Strong

    发明人： Kanak B. Agarwal ,  Nazmul Habib ,  Jerry D. Hayes ,  John Greg Massey ,  Alvin W. Strong

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2621 ,  G01R31/3004

    摘要： A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed.

    摘要翻译： 一种方法和测试电路提供测量以帮助理解时变阈值电压变化，例如负偏压温度不稳定性和正偏压温度不稳定性。 为了在阈值变化的早期阶段提供精确的测量，电流产生电路与被测器件集成在衬底上，其可以是从器件阵列中选择的器件。 电流产生电路可以是响应于由测试系统提供的外部供应电流的电流镜。 可以包括电压源电路以保持晶体管的漏 - 源电压恒定，尽管不是必需的。 在测量阶段之前施加应力，其可以包括在应力消除之后的可控松弛周期。