公开(公告)号：US07345305B2

公开(公告)日：2008-03-18

申请号：US11248719

申请日：2005-10-12

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US06989282B2

公开(公告)日：2006-01-24

申请号：US10815418

申请日：2004-04-01

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US06448173B1

公开(公告)日：2002-09-10

申请号：US09589546

申请日：2000-06-07

申请人： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

发明人： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

摘要翻译： 一种能够可靠地生产铝互连的双镶嵌工艺，其通过常规RIE技术生产的铝互连件具有改善的电迁移特性。 特别地，双镶嵌工艺依赖于PVD-Ti / CVD-TiN阻挡层以产生显示出显着降低的饱和电阻水平和/或抑制电迁移的铝线，特别是在长于100微米的线中。 双镶嵌铝线的电迁移寿命很大程度上取决于材料和材料填充工艺条件。 重要的是，材料和加工的偏差可导致电迁移寿命低于铝RIE互连实现的寿命。 在一个示例中，高达2.5MA / cm 2的电流密度是诱导由于电迁移引起的统计上相关的失败数量所必需的。

公开(公告)号：US07247946B2

公开(公告)日：2007-07-24

申请号：US11037970

申请日：2005-01-18

申请人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

发明人： John Bruley ,  Roy A. Carruthers ,  Lynne Marie Gignac ,  Chao-Kun Hu ,  Eric Gerhard Liniger ,  Sandra Guy Malhotra ,  Stephen M. Rossnagel

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

摘要翻译： 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

公开(公告)号：US06436823B1

公开(公告)日：2002-08-20

申请号：US09679738

申请日：2000-10-05

申请人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

发明人： Cyril Cabral, Jr. ,  Chung-Ping Eng ,  Lynne Marie Gignac ,  Christian Lavoie ,  Patricia O'Neil ,  Kirk David Peterson ,  Tina Wagner ,  Yun-Yu Wang ,  Keith Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L2221/1078

摘要： A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

摘要翻译： 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法，而不形成含有Ti，Co和Si的厚非晶层以及形成的结构。 在该方法中，在金属硅化物层的顶部沉积Ti层之后，进行双相退火工艺，其中在不高于500℃的温度下在成形气体（或氨）中进行低温退火。 首先进行少于2小时，然后在不低于500℃的第二温度下在含氮气体（或氨）中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题，并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm，这使线路故障问题最小化。